Compact transistor pair layout and method thereof

Details Compact transistor pair layout and method thereof Compact transistor pair layout and method thereof

1991-11-04

1993-09-07

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257368, 257903, H01L 2701

Patent

active

052432033

ABSTRACT:
A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).

REFERENCES:
patent: 5001539 (1991-03-01), Inoue et al.
patent: 5034797 (1991-07-01), Yamanaka et al.
patent: 5095347 (1992-03-01), Kirsch
Complementary FET Memory Cell, IBM Technical Disclosures Bulletin, by R. R. Garnache, published May 1976.

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