Compact stacked electronic package

Details Compact stacked electronic package Compact stacked electronic package

2001-02-05

2003-07-08

Ngo, Hung V. (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C439S066000, C439S074000

Reexamination Certificate

active

06590159

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to high density, low profile electronic packages and, more particularly, to the packaging of high performance, high density semiconductors having impedance-controlled transmission line buses for maintaining high electrical performance.
BACKGROUND OF THE INVENTION
The current trend in electronic package design for use in high speed electronic systems is to provide high electrical performance, high density and highly reliable interconnections between various circuit devices, which form important parts of those systems. The system may be a computer, a telecommunications network device, a handheld “personal digital assistant”, medical equipment, or any other electronic equipment.
High reliability for such connections is essential due to potential end product failure, should vital misconnections of these devices occur. It is also very important that the interconnections be as dense as possible, use the least possible amount of real estate on the printed circuit board, and provide minimal impact on the printed circuit board wiring. In some cases, such as for laptop computers and handheld devices, it is very important that the height of the connectors and the auxiliary circuit members be as low as possible.
As system density and performance have increased so dramatically, so have the stringent specifications for interconnections. One way high electrical performance is manifested is in improved signal integrity. This can be accomplished by providing the interconnections with shielding that helps them to more closely match a desired system impedance. These demanding requirements, especially when coupled with the requirement for field-separability, have led to a wide variety of possible connector solutions.
Also, to assure effective repair, upgrade, and/or replacement of various components of the system (e.g., connectors, cards, chips, boards, modules, etc.), it is desirable that the connections be reworkable at the factory. It is also highly desirable in some cases that, within the final product, such connections be separable and reconnectable in the field. Such a capability is also desirable during the manufacturing process for such products in order to facilitate testing, for example.
A land grid array (LGA) is an example of such a connection in which each of two primarily parallel circuit elements to be connected has a plurality of contact points, arranged in a linear or two-dimensional array. An array of interconnection elements, known as an interposer, is placed between the two arrays to be connected, and provides the electrical connection between the contact points or pads. For even higher density interconnections, additional parallel circuit elements may be stacked and electrically connected through additional LGA connectors to create three-dimensional packages. In any case, since a retentive force is not inherent as in a pin-and-socket type interconnection, a clamping mechanism is needed to create the force necessary to ensure each contact member is compressed an appropriate amount during engagement to form the required interconnections to the circuit elements. While LGA interposers are implemented in many different ways, the implementations of most interest are those described in the aforementioned copending U.S. patent applications.
There have been many limitations to the successful implementation of high density, low profile, low cost, three dimensional electronic packages. Firstly, higher density packages were needed only for very high-end electronic applications such as supercomputers, where size, weight and cost were not issues. Secondly, high volume products such as personal computers were cost sensitive and had sufficient internal room which encouraged engineers to use existing electronic packages. Thirdly, portable and handheld devices were simple enough and too cost sensitive to demand higher density packaging technologies. Overall, the electronic package technology currently available has been unable to meet the stringent set of requirements listed above. It is believed that a high density, low profile, low cost, three dimensional electronic package would constitute a significant advancement in the art.
It is, therefore, an object of the invention to enhance the electrical interconnection art.
It is another object of the invention to provide a high density electronic package with improved electrical and mechanical performance and reliability.
It is an additional object of the invention to provide a high density electronic package that is low profile.
It is an additional object of the invention to provide a high density electronic package with improved manufacturability, lower cost and one that is factory reworkable.
It is an additional object of the invention to provide a high density electronic package that is light weight and provides a small, low profile form factor.
It is a still further object of the invention to provide a high density electronic package that is field separable.
SUMMARY OF THE INVENTION
The present invention provides a high density, low profile electronic package for high speed, high performance semiconductors. It includes a plurality of devices, circuit members and short interconnections between the circuit members for maintaining high electrical performance. Certain applications requiring high speed, impedance-controlled transmission line buses throughout the entire package. These include but are not limited to microprocessor and digital signal processor data buses, and high speed memory buses for products such as laptop and handheld computing and telecommunications devices. Circuit members include printed circuit boards and circuit modules, and may be formed from a wide variety of materials with unpacked or packed semiconductors attached directly to the circuit members. Through clamping means the package is at least factory reworkable and can be field separable. Thermal management structures may be included to maintain the high density devices within a reliable range of operating temperatures.


REFERENCES:
patent: 5134546 (1992-07-01), Izumi et al.
patent: 6354844 (2002-03-01), Coico et al.

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