Compact semiconductor package with integrated bypass...

Details Compact semiconductor package with integrated bypass... Compact semiconductor package with integrated bypass...

2008-12-08

2011-11-22

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C257S502000

Reexamination Certificate

active

08062932

ABSTRACT:
A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

REFERENCES:
patent: 6919644 (2005-07-01), Uchida
patent: 7776658 (2010-08-01), Liu et al.

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