Compact ROM with reduced access time

Details Compact ROM with reduced access time Compact ROM with reduced access time

1983-08-29

1985-10-01

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365203, G11C 1140

Patent

active

045450331

ABSTRACT:
The number of contact holes is reduced by fabricating the column select decode circuit as part of the array. The decode circuit includes four tiers of alternately arranged depletion mode and enhancement mode transistors, each tier receiving a different column address signal. The appropriate combination of signals connects a column of series connected driver transistors to the precharged control terminal of an isolation transistor. The output circuit of the isolation transistor is connected between the output line and ground. If all the driver transistors in the selected column are rendered conductive, the isolation transistor becomes non-conductive, permitting the output line to charge to a positive level.

REFERENCES:
patent: 4480320 (1984-10-01), Naiff
IEEE Journal of Solid State Circuits, vol. SC11, No. 3, Title "Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI", by Kawagoe et al.

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