Compact pipelined matrix multiplier utilizing encoding and shift

Details Compact pipelined matrix multiplier utilizing encoding and shift Compact pipelined matrix multiplier utilizing encoding and shift

1994-08-17

1999-02-02

Malzahn, David H.

Boots, shoes, and leggings

36476002, 36476004, G06F 752, G06F 1716

Patent

active

058674144

ABSTRACT:
A circuit and algorithm for multiplying three matrices includes plurality of processor element (PE) column. Each PE column includes a plurality of processor element (PE) units and each unit includes a data register for receiving and storing a plurality sets of numbers of a row of a first matrix and a corresponding column of a second matrix. Each of the PE units is connected to another PE units of the PE column sequentially transmitting the sets of numbers between the registers in a time progressive manner. Each of the PE units further includes a multiplication processing unit for receiving a plurality of bits of the sets of numbers processes the plurality of bits to generate a partial processing result At least one of the PE units using the partial processing result generates a multiplication of the sets of numbers whereby each of the PE column performs a matrix multiplication of a column of the second matrix. Since the number of PE columns is equal to the number of columns of the second matrix, the multiplication circuit thus performs a multiplication of the first matrix to the second matrix.

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