Optics: measuring and testing – For optical fiber or waveguide inspection
Reexamination Certificate
2001-04-26
2003-07-15
Nguyen, Tu T. (Department: 2877)
Optics: measuring and testing
For optical fiber or waveguide inspection
Reexamination Certificate
active
06594004
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an optical time domain reflectometer (hereinafter referred to as an OTDR) and, in particular, to an OTDR for inputting a light pulse into an optical fiber line path and finding an intensity variation of returned light from the optical fiber line path with respect to a time in which the OTDR adopts a technique for achieving an enhanced distance accuracy.
BACKGROUND ART
In the case where the test of a communication system using an optical fiber line path is carried out, use is made of an OTDR
10
having a structure as shown in FIG.
7
.
That is, this OTDR
10
is so configured as to input a light pulse from a light pulse generation section
12
through a directional couper
11
to an optical fiber line path
1
as a to-be-tested object connected to a connection terminal
10
a
, receive the light which is returned back from the optical fiber line path
1
at a light receiving unit
13
via-the directional coupler
11
, and, while sampling the receiving signal by an analog/digital (A/D) converter
14
with a predetermined frequency, convert it to a digital value.
And this OTDR
10
finds a digital value which is outputted from the A/D converter
14
until a predetermined time elapses from the inputting of the light pulse, as data representing the transmission characteristic of the optical fiber line path
1
.
It is to be noted that, in
FIG. 7
, a measurement control circuit
15
outputs a drive pulse Pd to the light pulse generation section
12
to allow a light pulse to exit in synchronism with the drive pulse Pd while, on the other hand, the control circuit
15
outputs a sampling pulse PS of a predetermined period to the A/D converter
14
a predetermined number of times to allow the sampling of a receiving signal.
In the OTDR
10
thus configured, a resolution as to the time determines a resolution as to the distance of the characteristic of the optical fiber line path
1
.
In order to make measurement with a high distance resolution it is necessary to make the period of the sampling pulse Ps of the A/D converter
14
smaller.
However, there is a limitation to the sampling speed of the A/D converter
14
and, in order to maintain the accuracy of the data higher, a problem arises from the fact that it is not preferable to increase the sampling speed up to its limit.
In order to solve this problem, the conventional OTDR
10
does the following.
First, in order to find the characteristic of one optical fiber line path
1
a drive pulse Pd of a predetermined width is outputted an M number of times (it is assumed that M=5) as shown in FIG.
8
A.
And, as shown in
FIGS. 8B-F
, respective N numbers of sampling pulses Ps (
1
), Ps (
2
), . . . , Ps (
5
) are outputted to the A/D converter
14
while delaying their output start timing by a predetermined time &Dgr;T (1/M of a period T of the sampling pulse Ps) with respect to the output timing of the drive pulse Pd at each number of times.
The system of obtaining a series of data by shifting the sampling start timing by “1/an integral number” of the period of the sampling pulse with respect to the analog signal repeatedly inputted with the same waveform is generally called as an interleave sampling.
By performing such sampling based on this interleave sampling it is possible to obtain data equivalent to the case when a signal received from the incidence of the light pulse into the optical fiber line path
1
until the passage of an N·T−&Dgr;T time is M·N times continuously sampled with a period &Dgr;T shorter than a period T of the sampling pulse PS, as shown in FIG.
8
G.
That is, the sampling speed of the A/D converter
14
can be made equivalent to that multiplied M times.
In order to relatively delay the output start timing of the sampling pulse Ps by a predetermined time &Dgr;T in this way, the conventional OTDR
10
includes the measurement control circuit
15
configured as shown in
FIGS. 9 and 10
.
In the structure as shown in
FIG. 9
, a clock signal generation circuit
16
generates a clock signal CKr of a predetermined period T as a reference.
This clock signal CKr is input to a drive pulse generation circuit
17
and to a plurality of delay elements
18
(
1
),
18
(
2
), . . . ,
18
(M).
The drive pulse generation circuit
17
is so configured that, upon receipt of a start signal for designating a measurement start, it outputs a drive pulse Pd of a predetermined time width, an M number of times, in synchronization with the clock signal CKr with a period longer than N times the period T of the clock signal CKr.
The delay elements
18
(
1
),
18
(
2
), . . . ,
18
(M) output the inputted clock signals CKr to the select circuit
19
while being delayed by 0, &Dgr;T, 2&Dgr;T/, . . . , (M−1) &Dgr;T.
The select circuit
19
selectively provides, as a sampling pulse Ps, an output out of these outputs of the delay elements
18
(
1
),
18
(
2
), . . . ,
18
(M) which is designated from a switching circuit
20
.
The switching circuit
20
sets the select circuit
19
in a non-select state until receiving a start signal and, upon receipt of the start signal, causes the select circuit
19
to select an output of the delay circuit
18
(
1
).
When, by doing so, an N number of sampling pulses Ps are outputted from the select circuit
19
, the switching circuit
20
again sets the select circuit
19
in a non-select state.
And the switching circuit
20
causes the output of the delay element
18
(
2
) to be selected by the select circuit
19
upon receipt of the next drive pulse as an output pulse.
By doing so, when a predetermined N number of sampling pulses Ps are outputted from the select circuit
19
, the switching circuit
20
again sets the select circuit
19
in a non-select state.
In the same way as set out above, the switching circuit
20
causes the select circuit
19
to select the outputs of the delay elements
18
(
3
), . . . ,
18
(M).
When the output of the last delay element
18
(M) is selected by the select circuit
19
and the predetermined number N of sampling pulses Ps are outputted, then the switching circuit
20
causes the select circuit
19
to be set to the non-select state, thus waiting for the inputting of the next start signal.
By the select operation by the switching circuit
20
of the delay elements
18
(
1
),
18
(
2
), . . . ,
18
(M) it is possible to provide respective N numbers of sampling pulses Ps (
1
), Ps (
2
), . . . , Ps (M), as shown in
FIGS. 8A
to G, to the A/D converter
14
while delaying the output start timing by a predetermined time &Dgr;T with respect to the output timing of the drive pulse Pd at each number of times.
In an arrangement shown in
FIG. 10
, a clock signal CKr outputted from a clock signal generation circuit
16
is divided by a frequency divider
21
into, for example, four frequency division parts which are inputted as a frequency divided signal CKd to an integrating circuit
22
.
The integrating circuit
22
integrates the frequency divided signal CKd and outputs a ramp function signal V (=&agr;t) for example, with a voltage V increasing from 0 volt in proportion (proportional constant &agr;) to a time t with its high level time point as a reference.
The ramp function signal V, together with a reference voltage Vr from a reference voltage generator
23
, is inputted to a comparator
24
where comparison is made between the ramp function signal V and the reference voltage Vr.
At a timing that the ramp function signal V coincides with the reference voltage Vr and the output of the comparator
24
is inverted, a drive pulse generation circuit
17
outputs a drive pulse Pd of a predetermined width while, on the other hand, a sampling pulse generation circuit
25
starts to output an N number of sampling pulses Ps in synchronization with the clock signal CKr.
Until receiving a start signal, the switching circuit
26
sets the reference voltage Vr which is outputted from the reference voltage generator
23
to a voltage higher than a maximal value of the ramp function signal V outputte
Anritsu Corporation
Frishauf Holtz Goodman & Chick P.C.
Nguyen Tu T.
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