Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-10-30
2002-10-22
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185070, C365S154000
Reexamination Certificate
active
06469930
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to nonvolatile circuits, and more particularly to nonvolatile circuits that may be programmed to recall one or more particular states.
BACKGROUND OF THE INVENTION
Integrated circuit devices may include volatile and nonvolatile circuit elements. As is well known, volatile circuit elements are typically not capable of retaining a particular state in the absence of power. In contrast, nonvolatile circuits can retain one of at least two states in the absence of power. Nonvolatile circuit elements may include, without limitation, various erasable programmable read-only-memory cells (such as EPROMs, conventional EEPROMs, and “flash” EEPROMs). A typical EPROM cell can take advantage of a charge storing structure, such as a floating gate, a charge storing dielectric and/or a charge-trapping interface of materials. Alternate nonvolatile structures may take advantage of other materials, such as ferroelectric materials, or the like.
One concern with many nonvolatile circuit elements can be variations in response over time. In particular, a nonvolatile circuit element may include a field effect transistor having a threshold voltage that may be set to at least two states. Such a field effect transistor may have a charge storing structure (e.g., a floating gate or charge storing dielectric), and can be programmed to one threshold voltage and erased to another threshold voltage. Typically, an erased threshold voltage is less than a programmed threshold voltage.
Unfortunately, a nonvolatile transistor threshold voltage can change over time. Such changes can arise due to “disturbs” caused by local fields generated on a device. In addition, charge may leak from a charge storing structure. If a threshold voltage changes a sufficient amount, an erased threshold may be misread as a programmed voltage, or vice versa.
Typically, conventional volatile circuits may provide a more rapid response than nonvolatile circuits. Thus, data may be written to conventional volatile circuit elements faster than it can be stored (programmed) into conventional nonvolatile circuit elements.
While conventional volatile circuits can typically operate with acceptable reliability, in most environments, it can be advantageous to add nonvolatile functionality to a circuit. For example, in some applications, a device may be subject to unwanted interruptions in power. In such a case, it may be advantageous to preserve a circuit state or pre-programmed data so that circuit operation may resume once power is returned.
One example of a circuit that may provide both rapid operation and a form of nonvolatility is a nonvolatile (NV) static random access memory (SRAM) cell. A NVSRAM cell may have data stored (or programmed). The NVSRAM cell may then operate in a conventional SRAM manner by receiving data values according to write operations and providing data values according to read operations.
Unlike volatile SRAM cells, a NVSRAM cell may further include a recall operation. In a recall operation, a NVSRAM cell can be forced to the state established in a previous store operation. Such an arrangement can allow stored data to be preserved in the event that power is interrupted. More particularly, if a power interruption is detected, a limited amount of back up power can be made available to store the current state of a volatile SRAM circuit in nonvolatile circuit elements.
One example of a conventional NVSRAM cell is shown in FIG.
6
and designated by the general reference character
600
. A conventional NVSRAM cell
600
may include a volatile section
602
and a nonvolatile section
604
. A volatile section
602
may include a conventional six-transistor (6-T) memory cell with cross-coupled complementary driver transistors
606
/
608
and
610
/
612
. A first data node
614
may be formed between drains of transistors
606
and
608
, while a second data node
616
may be formed between drains of transistors
610
and
612
. First and second data nodes (
614
and
616
) can store complementary data values that may be accessed by access transistors
618
and
620
.
A conventional NVSRAM cell
600
can differ from a typical SRAM cell in that complementary data nodes (
614
and
616
) may be connected to a nonvolatile portion
604
. Such an arrangement can enable a data value stored in a volatile section
602
to be programmed into a nonvolatile section
604
. Such programmed data in a nonvolatile section
604
may then be recalled into a volatile section
602
.
In an arrangement such as that shown in
FIG. 6
, a nonvolatile section
604
may include a pair of nonvolatile devices
622
and
624
that may be programmed to complementary states. More particularly, nonvolatile devices
622
and
624
can be silicon-oxide-nitride-oxide-silicon (SONOS) transistors that may be programmed to different threshold voltages. Nonvolatile devices (
622
and
624
) may be connected to a volatile section
602
by a load path that includes load devices
626
and
628
and a program path that includes program devices
630
and
632
.
A load path (
626
and
628
) may be used to connect nonvolatile devices (
622
and
624
) to a volatile section
602
in a recall operation. More particularly, nonvolatile devices
622
and
624
that are programmed to different threshold voltages can be connected to data nodes (
614
and
616
) so that one data node can be lower than the other as a power supply to the volatile section
602
is ramped up. A conventional NVSRAM
600
may thus rely on two nonvolatile devices (
622
and
624
) set to different states.
A program path (
630
and
632
) may be used to connect nonvolatile devices (
622
and
624
) to a volatile section
602
in a store operation. More particularly, nonvolatile devices
622
and
624
may be initially erased. Complementary values at data nodes (
614
and
616
) may then be used to program nonvolatile devices
624
or
622
, respectively, to different threshold voltages.
As shown in
FIG. 6
, a program path (
630
and
632
) connection to data nodes
616
and
614
, respectively, can have a crossover with respect to a load path (
626
and
628
) to data nodes (
614
and
616
). Such an arrangement may be included because a set of data node values used to program nonvolatile devices (
622
or
624
) can result in an opposite set of data values being recalled from the nonvolatile devices (
622
or
624
).
A nonvolatile section
604
may also include programming devices
634
and
636
, which can connect a programming voltage to nonvolatile devices (
622
and
624
) in a program operation and a ground connection during a non-volatile recall.
A drawback to conventional arrangements, like that shown in
FIG. 6
, can be the number of devices included in the circuit. As noted above, a conventional NVSRAM
600
may include two nonvolatile devices as it can rely on programming such devices to different states. Further, because two nonvolatile devices can be used, a program path (
630
and
632
) and load path (
626
and
628
) may include two devices. Such devices can increase the overall area required for a NVSRAM cell. A larger cell area can work against the goal of reducing overall die size. Smaller die sizes are desirable, as they can allow for more economical manufacturing of integrated circuits.
It is understood that a NVSRAM
600
could also include additional circuit elements, including but not limited to “hold” devices (
634
and
636
) that may isolate p-channel driver devices (
606
and
610
) from their corresponding n-channel driver devices (
608
and
612
), an equalization device for equalizing data nodes (
614
and
616
), and/or dual port circuitry that allows additional access to one or both data nodes (
614
and
616
).
Having described a “differential” approach to a NVSRAM (i..e., two nonvolatile devices programmed to different states), a “single-side” approach to a NVSRAM will now be described.
Referring now to
FIG. 7
, another conventional NVSRAM cell is designated by the general reference character
700
, and is shown to in
Cypress Semiconductor Corporation
Lebentritt Michael S.
Nguyen Tuan T.
Sako Bradley T.
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