Compact non-volatile memory cell and array system

Details Compact non-volatile memory cell and array system Compact non-volatile memory cell and array system

2007-08-28

2007-08-28

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185280

Reexamination Certificate

active

11084213

ABSTRACT:
NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.

REFERENCES:
patent: 6865128 (2005-03-01), Kanai
patent: 2006/0077737 (2006-04-01), Ooishi
patent: 2006/0209598 (2006-09-01), Wang et al.

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