Compact non-volatile memory array with reduced disturb

Details Compact non-volatile memory array with reduced disturb Compact non-volatile memory array with reduced disturb

2007-01-09

2007-01-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S185050

Reexamination Certificate

active

11068625

ABSTRACT:
A non-volatile memory (NVM) array is made of NVM cells that have a floating gate transistor and a select transistor in which the floating gate transistor requires only a single layer of polysilicon. Adjacent cells are arranged so that the floating gates are staggered rather than being in the same line. This results in being able to put the cells closer together because of the reduction of the significance of what is commonly called poly-to-poly spacing. In this case, the termination of one floating gate is not lined-up with the floating gate of the adjacent NVM cell in the same row. Adjacent memory cells in the same column are made to have different configurations from each other which results in the floating gates in adjacent columns not being aligned, thus avoiding the poly-to-poly spacing limitation.

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Lee, Kung-Hong, “New Single-poly EEPROM with Cell Size down to 8F2for High Density Embedded Nonvolatile Memory Applications”, 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 93-94.

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