Compact MPEG data processing circuit and method of...

Details Compact MPEG data processing circuit and method of... Compact MPEG data processing circuit and method of...

2007-03-27

2007-03-27

Philippe, Gims (Department: 2621)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240250

Reexamination Certificate

active

10053184

ABSTRACT:
In an MPEG data processing circuit, inputted MPEG system stream is divided into a data block to be processed (for example, video elementary data portion) and a data block to be not processed (for example, non-video elementary data portion). The data to be processed are stored one by one in a primary storing section (a barrel shifter) while the numbers of data stored in the primary storing section or the data to be not processed are stored one by one in a secondary storing section (a FIFO buffer), responsive to kinds of blocks, in a predetermined storing form to be managed. After necessary data processing is conducted on the data of the block to be processed, both the data block to be processed and the data block to be not processed are finally combined to each other to be outputted as an MPEG system stream.

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Japanese Office Action issued Jun. 8, 2004 (w/ English translation of relevant portions).

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