Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-07-12
2011-07-12
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S050000, C716S100000, C716S106000, C716S108000, C716S111000, C716S112000, C716S113000, C716S132000, C716S136000, C703S004000, C703S013000, C703S015000
Reexamination Certificate
active
07979815
ABSTRACT:
A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.
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Chidambarrao Dureseti
Davidson Gerald M.
Hyde Paul A.
McCullen Judith H.
Narasimha Shreesh
Abate Esq. Joseph P.
International Business Machines - Corporation
Rossoshek Helen
Scully , Scott, Murphy & Presser, P.C.
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