Compact low power complement FETs

Details Compact low power complement FETs Compact low power complement FETs

1999-03-01

2001-03-13

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S368000, C257S369000, C257S371000, C438S199000

Reexamination Certificate

active

06201267

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to semi-conductor devices. More particularly, the present invention relates to complementary FETs.
2. Background Information
Field Effect Transistors (FETs), and in particular, CMOS (complementary metal oxide semi-conductor) FETs, have become the workhorse of integrated circuits in recent years. The principal advantage of CMOS transistors over other transistors is their much lower power dissipation. As one skilled in the art will appreciate, a CMOS device includes both an N-Channel MOSFET and P-Channel MOSFET. When the input (gate) voltage is high, the NMOS device is turned on and the PMOS device turns off; and when the input voltage is low, the PMOS device turns on and the NMOS device turns off. This is the basic mode of operation of complementary switches.
FIG. 1
depicts a cross-section of a conventional complementary Thin Film Transistor (TFT)
10
. A complementary TFT is made by connecting an N-Channel TFT and P-Channel TFT. The N-Channel TFT is separated from the P-Channel TFT by a minimum distance specified by design rules to minimize interaction between the two transistors.
The complementary TFT
10
is created on a glass substrate
12
. A buffer layer
14
of silicon dioxide prevents contaminants from the glass substrate from entering the active region. A layer of polycrystalline silicon (“polysilicon”) is patterned into active regions
16
and
18
. A layer of oxide
20
(gate insulator) separates the active regions from their respective gates
22
and
24
. The implantation of an N-type impurity in active region
16
defines source/drain regions
26
and
28
. A P-type impurity implanted in active region
18
defines source/drain regions
30
and
32
for the PMOS transistor. One skilled in the art will understand that the above description is merely one example of a method of making a CMOS TFT.
A second exemplary complementary FET structure is shown in
FIG. 2. A
complementary Heterostructure Insulated Gate Field Effect Transistor (c-HIGFET)
34
is shown in cross-section in FIG.
2
. As one skilled in the art will appreciate, a c-HIGFET uses a wide bandgap semiconductor barrier layer, instead of silicon dioxide used in the CMOS device
10
of FIG.
1
. The advantage of such a transistor is the high mobility of carriers, due to the reduced impurity and surface scattering.
A wide bandgap semiconductor
38
is placed over narrow bandgap semiconductor
36
. As one skilled in the art will know, a “wide bandgap semiconductor” refers to a semiconductor with a bandgap of about 0.4 eV to about 6.2 eV, for example, AlGaAs. Gates
40
and
42
are separated as shown for the N-channel device and the P-channel device, respectively. An N-type impurity is implanted to create source/drain regions
44
and
46
, and similarly, a P-type impurity is implanted to create source/drain regions
48
and
50
. Gates
40
and
42
comprise a Schottky metal.
The complementary transistors of FIG.
1
and
FIG. 2
, though useful advances in the semiconductor field, have their limitations. As an initial matter, the side-by-side design occupies more space than necessary, wasting the space between the N-channel device and the P-channel device. In addition, power dissipation is quite high, posing a constraint on low power applications.
SUMMARY OF THE INVENTION
Briefly, the present invention satisfies the need for a compact complementary FET design that dissipates less power by providing, among additional features, a complementary FET device with a stacked design, where the angle between the source/drain contacts for the—and P-channel devices is nonzero.
In accordance with the above, it is an object of the present invention to provide a complementary FET occupying less space than traditional side-by-side designs.
It is another object of the present invention to provide a complementary FET dissipating less power than conventional side-by-side designs.
The present invention provides, in a first aspect, a semiconductor device, comprising a first Field Effect Transistor (FET), e.g., a P-channel FET, having a first gate, a first channel region and a first source/drain pair, and a second FET, e.g., an N-channel FET, complementary to and vertically adjacent the first FET and having a second gate separate from the first gate, a second channel region and a second source/drain pair. The angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees, and the first channel region and the second channel region are situated between the first gate and the second gate.
The present invention provides, in a second aspect, a semiconductor device, comprising a first FET, e.g., a P-channel FET, having a first channel region and a first source/drain pair, and a second FET, e.g., an N-channel FET, complementary to and vertically adjacent the first FET and having a second source/drain pair and a second channel region. The semiconductor device further comprises at least one gate common to the first and second FETs. The angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.
The present invention provides, in a third aspect, a semiconductor device, comprising an insulating substrate, a first FET on the insulating substrate having a first source/drain pair and comprising one of P-type polysilicon and N-type polysilicon, and a second FET also on the substrate having a second source/drain pair comprising the other of P-type polysilicon and N-type polysilicon. The semiconductor device further comprises a gate common to both FETs, and a channel region common to both FETs comprising intrinsic polysilicon. An angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.
The present invention provides, in a fourth aspect, a semiconductor device, comprising a semi-insulating substrate, a narrow bandgap semiconductor layer on the semi-insulating substrate, a wide bandgap semiconductor layer on the narrow bandgap semiconductor layer, a first FET on the wide bandgap semiconductor layer having a first source/drain pair comprising one of a P-type narrow bandgap semiconductor material and an N-type narrow bandgap semiconductor material, and a second FET on the wide bandgap semiconductor layer having a second source/drain pair comprising the other of P-type narrow bandgap semiconductor material and N-type narrow bandgap semiconductor material. The semiconductor device further comprises a gate and a channel region common to both FETs. The channel region comprises unintentionally doped InGaAs, and the angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.
These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.


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