Compact integrated circuit with memory array

Details Compact integrated circuit with memory array Compact integrated circuit with memory array

2001-11-26

2003-09-16

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06621756

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compact integrated circuit with memory arrays, and more particularly to a compact integrated circuit with memory arrays, shared select transistors and distributed drivers of word line decoder (XDEC).
2. Description of the Related Art
With goals toward increased performance and higher density, various integrated circuit design approaches are known for memory devices such as EPROM, ROM, and other types including electrically-erasable programmable read-only-memory (EEPROM) and flash memory. While modern design approach achieves substantial density and performance, improvements are still desirable. Particularly, array overheads resulting from bank select area, XDECs and YMUXs are necessarily reduced. In the bank select area, the array of bank select transistors present a majority of the overhead. Currently, based on 0.5 micron technology, the bank select area is ⅓ of the memory cell area.
FIG. 1
shows a portion of a conventional array having two banks. As shown in
FIG. 1
, bank
1
has select lines
108
a
-
108
d
(SEL
00
-SEL
03
), select transistors
106
a
-
106
h
and 32 word lines, wherein WL
01
-WL
30
are omitted for simplicity and each word line such as word line
110
a
(WL
00
) and word line
110
b
(WL
31
) is coupled to a row of identical memory cells. Global bit lines
102
a
-
102
d
and local bit lines
104
a
-
104
h
are also shown in FIG.
1
. It is noted that bank
2
is identical to bank
1
. In the operation of this array, for example, in the access of memory cell
112
, word line
110
a
, local bit lines
104
b
and
104
c
are selected, and local bit lines
104
b
and
104
c
electrically connect global bit lines
102
b
and
102
a
through select transistor
106
e
and
106
b
respectively. Thus if memory cell
112
is selected, a high voltage signal (Logic Level “1”)from XDEC is applied to word line
110
a
, global bit lines
102
a
and
102
b
are selected by YMUX, select lines
108
b
and
108
c
are activated by select line decoders to activate select transistors
106
b
and
106
e
so that local bit line
104
b
can electrically connect global bit line
102
b
and local bit line
104
c can electrically connects global bit line
102
a
. The select areas shown in
FIG. 1
present large overhead and the chip area occupied by the select transistors is not utilized well. Thus it is obvious that the select areas must be further shrunk for upgrading the chip integration.
Conventional layout also presents large overhead.
FIG. 2
shows a conventional driver placement in a periphery region of a conventional integrated circuit layout. Decoder or driver
210
a
is used to drive a row of memory cells similar to the row of memory cells shown in
FIG. 1
in memory cell area
208
via word line
214
a
. Select word lines
216
a
-
216
d
(sw
10
-sw
13
) are also shown in FIG.
2
. Drivers
210
b
-
210
d
are separately used to drive three rows of memory cells in memory cell area
208
via word lines
214
b
-
214
d
. Similarly, other identical drivers arrayed below are separately used to drive the rest row of memory cells in memory cell area
208
. Pre-decoder area
202
inputs pre-decoded address signal xp
0
to drivers
210
a
-
210
d
via signal line
212
and pre-decoded address signal xp
1
-xp
7
to the identical drivers arrayed below via the signal lines identical to word line
212
. As shown in
FIG. 2
, each driver drives a row of memory cells in memory cell area
208
via a word line and all the 32 word lines pass transfer area
204
into memory cell area
208
. Transfer area
204
is necessary because the pitches or thicknesses of lead lines such as polysilicon word lines in periphery region and in memory cell region are different. The word lines must shrink or arrange closer before entering memory cell area
208
, and the shrink of the word lines occupy additional chip area as transfer area
204
shown in FIG.
2
. Select area
206
is similar to the select area shown in FIG.
1
. It is clear that transfer area
204
presents large overhead resulting from the pass and shrink of the word lines. Furthermore, as the process scale advances further, the reduction of a memory cell area would be unavoidable. It will be very difficult to place so many drivers into one memory cell area if maintaining a scheme of one driver driving one word line is still necessary.
In view of the drawbacks mentioned with the prior art layout, there is a continued need to develop new and improved layout that overcome the disadvantages associated with prior art layout. The requirements of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to reduce the overhead of integrated circuit resulting from the select areas.
It is another object of this invention to provide an improved integrated circuit layout with smaller transfer areas.
It is a further object of this invention to provide an integrated circuit layout with high integration.
To achieve these objects, and in accordance with the purpose of the invention, the invention provide an integrated circuit with a memory array, said integrated circuit comprising: a plurality of banks, a plurality of word lines, a plurality of local bit lines, a plurality of coupled select transistors arranged between two adjacent said banks, a plurality of global bit lines and a plurality of select lines. Each said bank comprises a plurality of memory cells arranged in rows and columns and each said word line couples each said row of memory cells. Each said local bit line couples said memory cells arranged in the same column of two adjacent said banks and each said select transistor is used to select said memory cells arranged in same column of two adjacent said banks via said local bit line. Said select line couples said select transistors of said coupled select transistors and said global bit line couples said coupled select transistors.
The invention also provides an integrated circuit with distributed drivers of XDEC, the integrated circuit comprises a pre-decoder area, a plurality of driver areas, wherein each said driver area is pre-decoded by said pre-decoder area, and a plurality of memory array areas, wherein each said memory array area has two said driver areas on both sides of each said memory array area to drive each said memory array area.
In another embodiment of this invention, the integrated circuit with distributed drivers of XDEC comprises a pre-decoder area, a plurality of driver areas, wherein each said driver area is pre-decoded by said pre-decoder area, and a plurality of memory array areas, wherein each said memory array area has two said driver areas on both sides of each said memory array area to drive each said memory array area, and each said memory array area comprises a plurality of memory cell areas and a plurality of select areas, wherein each said select area is between two adjacent said memory cell areas and has a plurality of coupled select transistors, and each said select transistor of said coupled select transistors couples two adjacent said memory cell areas.
The invention also provides a method of selecting a memory cell in the integrated circuit, the method comprises the steps of selecting two said select lines separately on two sides of a bank having said memory cell to decode said select transistors and select said bank, selecting two said global bit lines to select two said select transistors coupling said memory cell via two said local bit lines and selecting said word line coupling said memory cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5701269 (1997-12-01), Fujii
patent: 6047352 (2000-04-01), Lakhani et al.
patent: 6058053 (2000-05-01), Tsuji et al.
patent: 6339358 (2002-01-01), Horiguchi et al.
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp.

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