Compact glitchless M of N decoder circuit for digital to analog

Details Compact glitchless M of N decoder circuit for digital to analog Compact glitchless M of N decoder circuit for digital to analog

1993-01-22

1994-07-05

Young, Brian K.

Coded data generation or conversion

Digital code to digital code converters

To or from 'n' out of 'm' codes

H03M 720

Patent

active

053271289

ABSTRACT:
An M of N decoder circuit includes N output terminals, log.sub.2 (n+1) logic input terminals, two voltage input terminals, and (N+1)log.sub.2 (N+1) pass transistors, each having a gate connected to one of the logic input terminals, a source connected to one of a voltage input terminal and an output terminal, and a drain connected to one of said output terminals, each of the pass transistors for passing a voltage signal from source to drain when the gate has applied to it one logic level and for not passing said voltage signal when the gate has applied to a different logic level. More particularly, half of the pass transistors are of one conduction type and half of the pass transistors are of an opposite conduction type. The gates of N+1 pass transistors are connected to each of the log.sub.2 (M+1) input terminals. For i =0 to log.sub.2 (N+1)-1, pass transistors of one conduction type whose gates are connected to an i-th input terminal are connected in groups of 2.sup.i, and pass transistors of the opposite conduction type whose gates are connect to the i-th input terminal are also connected in groups of 2.sup.i.

REFERENCES:
patent: 4584567 (1986-04-01), Kinghorn
patent: 4633220 (1986-12-01), Burgess

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