Compact gate array

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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Details

257206, 257211, H01L 2710

Patent

active

057930686

ABSTRACT:
The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that is spaced with respect to a columns (28) of adjacent rows at which a contact exists. A plurality of gate conductors (35-42) are arranged to circumnavigate successive contacts (20,21) of adjacent rows on opposite sides in a serpentine patterns, preferably that follow partially circular paths. The contacts (20,21) are substantially circular in cross section, and may be provided with cap (32) on each that may also have a substantially circular cross section. The contacts (20-21) are spaced with a predetermined pitch and the gate conductors (35-42) have a width that defines transistor channels between adjacent contacts. The width of the conductors (35-42) allows the conductors to pass in proximity to the contacts (20-21) with a predetermined spacing. The gate array (10) may have in the substrate a second doped region (15) of an opposite conductivity type from a conductivity type of the first doped region (14). A gate array similar to that constructed above the first doped region is constructed above the second doped region to enable diverse logic circuits to be constructed by selective interconnections among selected contact and gate conductors (50,51).

REFERENCES:
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4807080 (1989-02-01), Clark
patent: 5146306 (1992-09-01), Ferry et al.
patent: 5292678 (1994-03-01), Dhong et al.
patent: 5517041 (1996-05-01), Torii et al.
"Source/Drain Personalization of High Density CMOS Read-Only Store", IBM Technical Disclosure Bulletin, vol. 28, No. 11, Apr. 1986.

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