Compact galois field multiplier

Details Compact galois field multiplier Compact galois field multiplier

1987-10-26

1989-07-11

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 700, G06F 1500

Patent

active

048478016

ABSTRACT:
Multiplication of two mq-bit bytes (in GF2.sup.mq) is reduced modulus an irreducible polynomial in GF2.sup.m of degree q to multiplication among two sets of q m bit bytes (in GF2.sup.m) in order to simplify hardware and reduce costs, by distributing the computation among a small number of programmable read only memories (PROMs) and adders.

REFERENCES:
patent: 4251875 (1981-02-01), Marver et al.
patent: 4745568 (1988-05-01), Onyszchuk et al.
Ellison et al., "Galois Logic Design", Prepared for the Air Force, Cambridge Research Lab., Air Force Systs. Commd., USAF, 1970.
Marver, "Sequential Galois Multipliers", Aug. 1977, Prepared for Office of Naval Research, Contract #W00014-77-C-0192.

Affiliated with

Also associated with

Rating

Compact galois field multiplier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compact galois field multiplier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact galois field multiplier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-442167