Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
1998-12-18
2002-10-29
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S058000, C377S028000
Reexamination Certificate
active
06473722
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a fault detecting system, particularly to the fault detecting system for use in an apparatus having a storing unit that is reset to a certain value at the time of initialization.
Conventionally, fault detection has been carried out for various kinds of apparatus such as an extended adapter board mounted on a personal computer. Some fault detections are carried out by constantly monitoring the apparatus through a parity check or a duplicated circuit. Other fault detections are carried out by judging whether or not a response is sent, for example, from the extended adaptor board at the time of starting up the personal computer.
An example of a method of the fault detection using the above-mentioned parity check is exemplified, as a first prior art, in unexamined Japanese Patent Publication No. Sho 58-169253, namely 169253/1983. In the first prior art, a parity bit is added to data so that the number of ones (“on” bits) within a group of data may become an even number (even parity check) or an odd number (odd parity check). The parity bit and the data are stored together in a storage unit. The fault detection is carried out by checking whether or not the number of ones is even or odd when the parity bit and the data are read from the storing unit. However, a method used in the first prior art requires not only a hardware unit for storing the parity bit but also a hardware unit for checking whether or not the number of ones indicate a predetermined even or odd parity. As a result, the hardware of the fault detection system in the first prior art inevitably becomes large in size or complex.
Furthermore, an example of a method of the fault detection using the above-mentioned duplicated circuit is disclosed, as a second prior art, in unexamined Japanese Patent Publication No. Sho 63-126041, namely, 126041/1988. In the second prior art, the fault detection system has a couple of circuits, each having the same function. Fault detection is carried out by checking if the outputs of the circuits is the same when the same input is applied. However, a method used in the second prior art requires twice the circuitry as that of a circuit for achieving the function alone.
Moreover, another example of a method of fault detection carried out by judging whether or not a response is sent from the extended adaptor board at the time of starting up the personal computer is disclosed, as a third prior art, in unexamined Japanese Patent Publication No. Hei 4-98555, namely 98555/1992. In the third prior art, a signal or a command for expecting a specific response is produced from a main board at the time of starting up the personal computer. Accordingly, the fault detection is carried out by checking whether or not the expected response is returned from the extended adaptor board. By a method used in the third prior art, it is possible to detect a fault of a function from the response in the extended adaptor board. However, it is not possible to detect faults for another function having no relation to the response for the original in the extended adaptor board.
Thus, the methods of the first and the second prior arts of always detecting faults through a parity check or a duplicated circuit are superior in detection accuracy to the method of the third prior art. However, the hardware used for detecting faults inevitably become large in size and adds complexity. A problem of increased cost is incurred to put the methods of the first and the second prior arts into practice.
On the other hand, in the method of the third prior art of judging whether or not a proper response is returned from the extended adaptor board, the fault detection system is realized with comparatively simple hardware. However, it is only possible to detect a fault for the circuit capable of returning the response. Accordingly, it is difficult to detect all the faults generated in an entire apparatus.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a compact fault detection system which is capable of detecting almost all faults generated in an entire apparatus.
Other objects of the present invention will become clear as the description proceeds.
According to an aspect of the present invention, there is provided a fault detection system for use in an apparatus, comprising: storing means which store data and which are reset to have a predetermined value when the apparatus is initialized; an objective circuit which is supplied with the data stored in the storing means as input data and which produces an output; and fault detection means for detecting whether or not the output is corresponding to the predetermined value when the storing means are reset; the fault detection means deciding that the objective circuit has a fault when the output is not corresponding to the predetermined value.
The fault detection means may not detect whether or not the output is corresponding to the predetermined value when the storing means are not reset.
The objective circuit may be an operator which outputs specific data univocally determined by input data inputted thereinto.
The objective circuit may be a combinational circuit which outputs specific data univocally determined by input data inputted thereinto.
According to another aspect of the present invention, there is provided a fault detection system for use in an apparatus, comprising: storing means which store data and which are reset to have a predetermined value when the apparatus is initialized; a plurality of objective circuits which are suppled with the data stored in the storing means as input data and which produce outputs, respectively; and fault detection means for detecting whether or not the outputs are corresponding to the predetermined value, respectively when the storing means are reset; the fault detection means deciding that the plurality of objective circuits have a fault when any one of the outputs is not corresponding to the predetermined value.
The fault detection mans may not detect whether or not the outputs are corresponding to the predetermined value, respectively when the storing means are not reset.
One of a plurality of the objective circuits may be an operator which outputs specific data univocally determined by input data inputted thereinto.
One of a plurality of the objective circuits may be a combinational circuit which outputs specific data univocally determined by input data inputted thereinto.
REFERENCES:
patent: 3555255 (1971-01-01), Toy et al.
patent: 3831148 (1974-08-01), Greenwald et al.
patent: 5440604 (1995-08-01), De Subijana et al.
patent: 5448722 (1995-09-01), Lynne et al.
patent: 5574856 (1996-11-01), Morgan et al.
patent: 5627965 (1997-05-01), Liddell et al.
patent: 58-169253 (1983-10-01), None
patent: 63-126041 (1988-05-01), None
patent: 4-98555 (1992-03-01), None
John Markus, “Sourcebook of electronic circuits”, 1968, p. 152.
Charioui Mohamed
Dickstein, Shapiro, Morin & Oshinsky L.L.P.
Hoff Marc S.
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