Compact dual function adder

Details Compact dual function adder Compact dual function adder

1994-05-17

1996-04-02

Envall, Jr., Roy N.

Boots, shoes, and leggings

364770, 364786, 364787, G06F 750

Patent

active

055046983

ABSTRACT:
A compact dual function adder circuit for providing both an addition operation for adding an input m-bit word to an input n-bit word, wherein m<n, and an increment operation for incrementing the input n-bit word, the dual function adder comprising a n-bit incrementer circuit, wherein the n-bit incrementer includes a first m-bit incrementer and a second n-m)-bit incrementer to provide a n-bit incrementer output sum. The n-bit incrementer output sum comprises an m-bit incrementer output sum from the m-bit incrementer and a n-m)-bit incrementer output sum from the n-m)-bit incrementer. The compact dual function adder also comprises a combined adder circuit, the combined adder comprising a first m-bit full-adder, a n-m)-bit decrementer, and an adder select logic circuit, wherein the adder select logic receives an adder carryout bit from the m-bit full-adder and a bit<15> of the input m-bit word to control an operation of the adder select logic to generate either an increment operation, a decrement operation, or a bypass operation.

REFERENCES:
patent: 4224668 (1980-09-01), Peters et al.
patent: 4309753 (1982-01-01), Negi et al.
patent: 4723258 (1988-02-01), Tanaka et al.
patent: 4761760 (1988-08-01), Tomoji
patent: 5027310 (1991-06-01), Dalrymple

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