Dynamic information storage or retrieval – Control of storage or retrieval operation by a control... – Control of information signal processing channel
Reexamination Certificate
2002-07-31
2004-02-10
Hindi, Nabil (Department: 2655)
Dynamic information storage or retrieval
Control of storage or retrieval operation by a control...
Control of information signal processing channel
C369S053150
Reexamination Certificate
active
06690630
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a compact disc decoder, and more specifically, to a compact disc decoder that uses an input error flag to correct address errors in header data read from the compact disc.
2. Description of the Prior Art
Compact discs (CDs) are commonly produced using two formats: CD Read Only Memory (CD-ROM) and CD Digital Audio (CD-DA). In each of these formats, digital data is read off of the CD, and processed by a CD-ROM drive. In addition, CD-DA discs may also be played in an audio CD player. In U.S. Pat. No. 5,621,743 entitled “CD-ROM Decoder for Correcting Errors in Header Data”, Tomisawa discloses a prior art CD-ROM decoder, which is included herein by reference.
Please refer to FIG.
1
.
FIG. 1
is a functional block diagram of a CD drive that is capable of decoding CD-ROM and CD-DA discs according to the prior art. A pickup unit
2
receives reflected light of a laser beam irradiated to a compact disc
1
, converts the intensity of the reflected light into a voltage signal representing the intensity value, and supplies the signal to an analog signal processing unit
3
. The analog signal processing unit
3
reads out digital data written in the compact disc
1
from the input signal, and outputs, in series, the digital data having a format similar to the given format. The output from the analog signal processing unit
3
is connected to an input of a digital signal processing unit
4
, which carries out processing of the digital data input from the analog signal processing unit
3
in accordance with the proper digital data format, CD-ROM format or CD-DA format. The signal processing in the digital signal processing unit
4
maintains compatibility with a digital audio CD system, and includes, for example, demodulation of 14 bit digital data to 8 bit data and code error detection/correction based on Reed-Solomon code. A CD-ROM decoder
5
and a CD-DA decoder
39
respectively provide additional code error correction for the CD-ROM data or CD-DA data fed from the digital signal processing unit
4
and transfer the CD-ROM or CD-DA data, which has substantially no errors, to a host computer. A buffer RAM
6
is connected to the CD-ROM decoder
5
and the CD-DA decoder
39
to temporarily store the CD-ROM or CD-DA data, which has been supplied from the digital signal processing unit
4
to the CD-ROM decoder
5
or the CD-DA decoder
39
, for a given period. A control micro computer
7
controls operation of the analog signal processing unit
3
, digital signal processing unit
4
, CD-ROM decoder
5
, and CD-DA decoder
39
in accordance with the operation programs so that each unit carries out the respective processing at the correct time.
Please refer to FIG.
2
.
FIG. 2
shows a typical data format for a sector of conventional CD data. The CD data output from the digital signal processing unit
4
shown in
FIG. 1
is divided into a number of sectors, and each sector is 2352 bytes and includes a synchronization signal (12 bytes), header (4 bytes) and user data (2336 bytes) as shown in
FIG. 2
, and as is well known in the art.
FIG. 3
is a functional block diagram of the conventional CD-ROM decoder
5
. A descramble circuit
11
provides descramble processing for the 2340 bytes of the 2352 bytes (1 sector) of CD ROM data input, disregarding the 12 byte synchronization signal, and outputs data which is recovered to be a given format. A write buffer
12
extracts 2336 bytes of data (hereinafter referred to as user data) from the data output from the descramble circuit
11
and writes the user data through a first data bus
16
into the buffer RAM
6
. A header register
13
takes in 4 bytes of the data output from the descramble circuit
11
and transfers the header information via a second data bus
17
to the control micro computer
7
. A synchronization signal detection circuit
14
detects a 12 byte synchronization signal assigned to the leader portion of the respective sectors of the input data and supplies a timing signal representing the beginning of the sector's CD-ROM data input to an operation control circuit
25
, details of which will be described below. When the synchronization signal is not detected, data showing the detection error is fed to the control micro computer
7
via the second data bus
17
. An error flag register
15
extracts an error flag indicating that errors are still left after the error correction by the digital signal processing unit
4
arranged before the CD-ROM decoder
5
and transfers the information via the second data bus
17
to the control micro computer
7
.
A write address generator
18
generates a series of addresses at a constant cycling period to designate a write address of the CD-ROM data which is to be written into the buffer RAM
6
from the write buffer
12
. A leading address generator
19
receives an address of the buffer RAM
6
, to which the leader portion of the respective sectors is to be written, from the address generator
18
. After keeping the received addresses until completion of the writing operation for a sector of the CD-ROM data, the leading address generator
19
feeds the addresses to the first data bus
16
. The leading addresses are also fed to the control micro computer
7
via the second data bus
17
so as to produce preset data for a transfer address generator
21
. An error correction circuit
20
takes in the leading address data via the first data bus
16
and sequentially reads out, based on the address data, the CD-ROM data which was written into the buffer RAM
6
. The error correction circuit
20
then detects and corrects a code error on the basis of the error detection code (EDC) and error correction code (ECC), which have been set in the user data. When the data has been subjected to given error correction processing in the above described manner, it is again written into the buffer RAM
6
.
The transfer address generator
21
is loaded with the preset data corresponding to the leading address of the buffer RAM
6
, at which time the reading out of the CD-ROM data begins. In response to a command from a buffer controller
22
, the transfer address generator
21
generates a series of addresses beginning from an address corresponding to the preset data. The generated addresses are fed via the first data bus
16
to the buffer RAM
6
and used for the designation of the readout address of the CD-ROM data which has been subjected to the error correction processing. A transfer byte counter
23
is loaded with preset data representing the CD-ROM data to be read out from the buffer RAM
6
and then decrements (counts down) the preset data value every time a sector of the CD-ROM data is read out from the buffer RAM
6
. At the point when a given count is completed, the counter
23
supplies a stop command to the buffer controller
22
. A transfer buffer
24
receives, via the first data bus
16
, the CD-ROM data which has been read out in accordance with the address generated by the transfer address generator
21
and transfers the data to the host computer. Each preset data loaded on the transfer address generator
21
and transfer byte counter
23
, respectively, is generated by the control micro computer
7
based on the leading address fed from, the leading address generator
19
and a transfer command given by the host computer.
The operation control circuit
25
counts the time period taken for the completion of error correction made by the error correction circuit
20
, on the basis of a timing signal from the synchronization signal detection circuit
14
and generates another timing signal indicating the completion of the error correction operation. The error correction processing is carried out inside the error correction circuit
20
after taking in a sector of CD-ROM data from the buffer RAM
6
, during which the next one sector of CD-ROM data is being written in the buffer RAM
6
.
An interrupt command generator
26
receives either the timing signal from the operation control circuit
25
or the stop com
Hindi Nabil
Hsu Winston
MediaTek Inc.
LandOfFree
Compact disc decoder and method for correcting address... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compact disc decoder and method for correcting address..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact disc decoder and method for correcting address... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3329164