Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
2005-03-15
2005-03-15
Gibson, Randy W. (Department: 2841)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C368S113000, C368S120000
Reexamination Certificate
active
06868047
ABSTRACT:
A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.
REFERENCES:
patent: 4104590 (1978-08-01), Zhevnerov
patent: 4164648 (1979-08-01), Chu
patent: 4402081 (1983-08-01), Ichimiya et al.
patent: 5479415 (1995-12-01), Staiger
patent: 5694377 (1997-12-01), Kushnick
patent: 5872745 (1999-02-01), Murakami
patent: 6073259 (2000-06-01), Sartschev et al.
patent: 6246737 (2001-06-01), Kuglin
patent: 6285963 (2001-09-01), West
Mota, M. et al.: “A flexible multi-channel high-resolution time-to-digital converter ASIC”, 2000 IEEE Nuclear Science Symposium. Conference Record (Cat. No. OOCH37149), 2000 IEEE Nuclear Science Symposium. Conference Record, Lyon, France, Oct. 15-20, 2000, vol.2, pp. 9/155-9 189, XP002236607 2000, Piscataway, NJ, USA, IEEE, USA ISBN: 0-7803-6503-8, p. 9-155, p. 9-158.
Mota, M. et al: “A four-channel self-calibrating high-resolution time to digital converter” Electronics, Circuits and Systems, 1998, IEEE International Conference on Lisboa, Portugal Sep. 7-10, 1998, Piscataway, NJ, USA, IEEE, US, Sep. 7, 1998, pp. 409-412, XP010366204, ISBN: 0-7803-5008-1, p. 409, p. 410.
Christiansen J.: “An integrated high resolution CMOS timing generator based on an array of delay locked loops”, IEEE Jounal of Solid0State Circuits, IEEE Inc. New York, US, vol. 31, No. 7, Jul. 1, 1996, pp. 952-957, XP000632381, ISSN: 0018-9200, the whole document.
Rainer Geiges, et al., “A High Resolution TDC Subsystem,” IEEE Transactions on Nuclear Science, vol. 41, No. 1, Feb. 1, 1994.
M. Sugawara, et al. “A 2.5V 100MS/s 8bit ADC Using Pre-Linearization Input Buffer and Level Up DAC/Subtractor,” 1998 Symposium on VLSI Circuits Digest of Technical Papers, Aug. 1998.
J. Christiansen, “An Integrated CMOS 0.15 ns Digital Timing Generator for TDS's and Clock Distribution Systems,” Mar. 1995.
Piotr Dudek, et al., “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Transactions on Solid-State Circuits, vol. 35, No. 2, Feb. 2000.
Yasuo Arai, et al., “A CMOS Four-Channel X 1K Time Memory LSI with 1-ns/b Resolution,” IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992.
Andrew E. Stevens, et al., “A Time-to-Voltage Converter and Analog Memory for Colliding Beam Detectors,” IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989.
C. Thomas Gray, et al., “A Sampling Technique and Its CMOS Implementation with 1 Gb/s Bandwidth and 25 ps Resolution,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994.
Keunoh Park, et al., “20ps Resolution Time-to-Digital Converter for Digital Storage Oscilloscopes,” Sep. 1999.
Joonbae Park, et al., “An Auto-Ranging 50-210Mb/s Clock Recovery Circuit with a Time-to-Digital Converter,” 1999 IEEE International Solid-State Circuits Conference, Feb. 17, 1999.
Elvi Raisanen-Ruotsalainen, et al., “An Integrated Time-to-Ditigal Converter with 30-ps Single-Shot Precision,” IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000.
R. Rankinen, et al., “Time-to-Digital Conversion with 10 ps Single Shot Resolution,” 1991.
Elvi Raisanen-Ruotsalainen, et al., “A BiCMOS Time-to-Digital Converter with 30 ps Resolution,” 1999.
Elvi Raisanen-Ruotsalainen, et al., “A Low-Power CMOS Time-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1995.
Hideki Shirasu, et al., “A VME 32 Channel Pipeline TDC Module with TMC LSIs,” IEEE Transactions on Nuclear Science, vol. 43, No. 3, Jun. 1996.
J. Kalisz, et al, “Time-to-Digital Converter with Direct Coding and 100ps Resolution,” Electronics Letters, vol. 31, No. 19, Sep. 14, 1995.
Dinis M. Santos, et al., “A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip,” 1996.
Antti Mantyniemi, et al., “A High Resolution Digital CMOS Time-to-Digital Converter Based On Nested Delay Locked Loops,” 1999.
Timo E. Rahkonen, et al., “The Use of Stabilized CMOS Delay Lines for the Digitization of Short Time Intervals,” IEEE Journal of Solid-State Circuits, vol. 28, No. 8, Aug. 1993.
Timo Rahknone, et al., “Time Interval Measurements Using Integrated Tapped CMOS Delay Lines,” 1990.
P. Bailly, et al., “A 16-Channel Digital TDC Chip,”.
Vadim Gutnik, et al., “On-Chip Picosecond Time Measurement,” 2000 Symposium on VSLI Circuits Digest of Technical Papers, Apr. 2000.
Jozef Kalisz, et al., “Single-Chip Interpolating Time Counter With 200-ps Resolution and 43-s Range,” IEEE Transactions on Instrumentation and Measurement, vol. 46, No. 4, Aug. 1997.
C. Ljuslin, et al., “An Integrated 16-Channel CMOS Time to Digital Converter,” IEEE Transactions on Nuclear Science, vol. 41, No. 4, Aug. 1994.
Beomsup Kim, et al., “A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990.
“Misfire Analysis with Time Interval Analyzer,” Yokogawa Test and Measurement, wysiwyg://210/http://www.yokogawa.com/tm/appli/48/48misfire.html.
“Using FastFrame Segmented Memory,” Tektronix MBD: Applications, sysiyg://BODY.181/http://www.tektronix . . . easurement/App_Notes/dpo/fastframe/eng/.
Sartschev Ronald A.
Xu Jun
Gibson Randy W.
Phan Thanh S.
Teradyne Legal Department
Teradyne, Inc.
LandOfFree
Compact ATE with time stamp system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compact ATE with time stamp system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact ATE with time stamp system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3400613