Communications subsystem having a self-latching data monitor and

Details Communications subsystem having a self-latching data monitor and Communications subsystem having a self-latching data monitor and

1980-10-06

1983-07-12

Chan, Eddie P.

Boots, shoes, and leggings

34082506, 1791752C, G06F 305

Patent

active

043934617

ABSTRACT:
A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.

REFERENCES:
patent: 3348209 (1967-10-01), Brooks
patent: 4125872 (1978-11-01), Maxwell
patent: 4156796 (1979-05-01), O'Neal et al.
patent: 4156907 (1979-05-01), Rawlings et al.
patent: 4168532 (1979-09-01), Dempsey et al.
patent: 4254462 (1981-03-01), Raymond et al.

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