Communications receiver architectures and algorithms...

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Details

C375S240210, C375S345000, C375S350000

Reexamination Certificate

active

06993099

ABSTRACT:
A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.

REFERENCES:
patent: 5549111 (1996-08-01), Wright et al.
patent: 5552942 (1996-09-01), Ziperovich et al.
patent: 6167258 (2000-12-01), Schmidt et al.
patent: 6766289 (2004-07-01), Kandhadai et al.
Texas Instruments Product Bulletin “AC5 Octal-Port Central Office ADSL Chipset” 2000.

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