Multiplex communications – Wide area network – Packet switching
Patent
1993-09-21
1995-04-25
Safourek, Bendict V.
Multiplex communications
Wide area network
Packet switching
34082516, H04Q 518
Patent
active
054105374
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a communications installation having a central controller, a number of peripheral controllers and a multiplicity of peripheral modules.
In communications installations configured in this manner, the peripheral controllers handle tasks of layer 2 according to the so-called ISO layer model, that is to say they are responsible for identification and correction of transmission errors and signalling synchronization. At the same time, they control the control traffic to the central controller. In this arrangement, a fixed number of predetermined subscribers or exchange lines is allocated to each peripheral controller. This has the disadvantage that when peak loads occur in individual peripheral controllers, overloading can occur and, in consequence, the response times of these peripheral controllers become too long whilst other peripheral controllers are not used to capacity. This unequal usage of the peripheral controllers results from the fact that the respective number of peripheral controllers exclusively depends on the number of existing exchange circuits or connected subscribers and not on the actual traffic volume.
SUMMARY OF THE INVENTION
It is the object of the present invention to specify a communications installation of the abovementioned type in which overloading of individual peripheral controllers is avoided.
According to the invention, this object is achieved by a communications installation of the type initially mentioned, separate data lines, lines, the central controller, a separate data highway. respective usage factor, and event of high usage of one peripheral controller.
In the communications installation according to the invention, one or more peripheral controllers are activated in dependence on the respective traffic volume so that overloading of an individual peripheral controller is impossible. In addition, the communications installation according to the present invention has the advantage that only little prior effort has to be made in the initial setting-up of the installation since only the number of peripheral controllers needed in accordance with the maximum traffic volume to be expected must be provided. In a later upgrading of the installation or in a later extension for data traffic and packet switching, further peripheral controllers can then be installed.
BRIEF DESCRIPTION OF THE DRAWING
The features of the present invention which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages, may best be understood by reference to the following description taken in conjunction with the accompanying drawing, and in which:
The single Figure is a block diagram of a communication installation according to the present invention
DESCRIPTION OF THE PREFERRED EMBODIMENT
The communications installation shown in the single Figure has the central controller CCU, the peripheral controllers PCU--0 to, for example PCU 6--and peripheral modules SLM1 to SLMn, TM1, MoH and SIA. The peripheral modules SLM1 to SLMn are subscriber circuits and the modules TM(x) are line circuits. The subscriber circuits are used for implementing, for example, analog and digital subscriber interfaces. The respective module contains the corresponding circuits for detecting the respective terminal states and a device for injecting the ringing tone. The number of line circuits TM(x) in each case depends on the configuration level of the installation.
Furthermore, a circuit for charge metering SIA and a "music-on-hold" module MoH, by means of which music or announcements can be played to waiting subscribers, can be provided as a peripheral module.
The central controller CCU essentially has a central processor CP, a memory unit M, a timer device T and a clock generating circuit C. The individual units of the central controller CCU are connected to one another via the PCM data transmission lines HWY0 . . . HWY3.
The individual peripheral controllers CPU0 . . . CPU6, whi
REFERENCES:
patent: 4136333 (1979-01-01), Sumida et al.
patent: 4413335 (1983-11-01), Clements et al.
patent: 5166673 (1992-11-01), Herrmann et al.
patent: 5268898 (1993-12-01), Kazato
Niessner Gerhard
Seul Peter
Safourek Bendict V.
Siemens Aktiengesellschaft
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