Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
2000-07-31
2004-06-01
Sam, Phirin (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S395600, C370S395640, C370S465000
Reexamination Certificate
active
06744782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a communications device, method thereof, a communications system and a recording medium, and relates in particular to a communications device, method thereof, a communications system and a recording medium to transmit and receive information for control exceeding one byte.
2. Related Art
Decoders for applications utilizing digital audio and images, perform decoding for instance of data output from an information generator source such as encoders, and of encoded and recorded data, while synchronizing with a clock pulse. If the decoder were capable of controlling the information generator source, then the decoder could adjust the data rate of the data that was sent and thus be dependent only on the timing of the received data, and then decode the data, and display the image or reproduce the audio.
However, when data is sent to the decoder by way for instance of a network, and the decoder possesses no control of the information generator source, the information generator source and the decoder are operated by respective, independent system clocks. The encoding, transmission, receiving, decoding and display processing are therefore performed by the information source generator and decoder based on their respective system clocks. The system clocks in such cases, do not have a common clock to refer to, so that a deviation or discrepancy occurs between the respective system clock frequencies of the information generator source and the decoder.
In this way, when two system clocks are not synchronized, the data sent from the information generator source, and the data decoded by the decoder have different data rates, and the decoder receive buffer overflows or underflows and so the data that was sent is lost. Therefore, when image data for instance is being received, and an underflow occurs, the receiver must again display the frame.
One method to synchronize the decoder system clock with the information generator source system clock is by utilizing information showing the time (time stamp). In an MPEG transport stream, a PCR (Program Clock Reference) is used as a time stamp so that the respective system clocks can be synchronized with each other.
The concept of synchronization in the MPEG transport stream is shown in FIG.
1
. The information generator source (transmit side) is operated by a corresponding system clock
1
at a specified frequency. Fixed intervals are not required but the value of a counter counting each system clock
1
is latched at each period, and that counter value is sent to the decoder (receive side). This value is called the time stamp, and the decoder uses this value to synchronize its own system clock
2
with the system clock
1
of the information generator source. More specifically, the count value and the time stamp that was received, are compared in the decoder and based on the comparison results, the system clock
2
on the receive side is made to speed up or slow down.
Synchronization methods such as this are utilized in the MPEG-2 system layer (ISO/IEC13818-1) and ITU-T report. In MPEG-2, a 27 MHz system clock is used in the encoder and decoder. The structure of a system for transmitting data configured for MPEG-2 over a network is shown in FIG.
2
. The information generator source is for instance an encoder device such as the encoder
11
. The pre-encoded data is accumulated in a data storage device, and this data storage device can be used as the information generator source.
The MPEG-2 data generated in the encoder
11
is input to the system encoder
12
. The system encoder
12
adds a time stamp to the MPEG-2 data generated in the encoder
11
, packetizes the data, and performs multiplexing to generate an MPEG transport stream packet (hereafter called transport stream packet). An MPEG/ATM converter
13
converts the transport stream packet to ATM cells, and sends them to the receive side by way of the network
14
. The transport stream packet is susceptible to various effects of delay distortion inside the network
14
when sending to the receive side. The generation of the delay distortion in the ATM is related later on.
The transport stream (time stamp) containing delay distortion is packetized in the MPEG converter
15
, input to the system decoder
16
and processed in the system decoder
16
. The decoder system clock is reproduced from the time stamp in this way. A 27 MHz system clock is reproduced in the case of MPEG-2. The transport stream packet processing by the system decoder
16
is output to the decoder
17
where decoding into MPEG-2 data is performed.
Two streams referred to as the program stream and the transport stream are present in the MPEG-2 system layer. The program stream is available for systems without errors such as storage media. The transport stream is available for systems having errors such as communications. The time stamp in the program stream is referred to as the SCR (system clock reference) and is sent in periods within at least 0.7 seconds. The SCR time stamp is incorporated into the program stream packet and is only present in packets for transmitting the SCR. The time stamp in the transport packet stream is a PCR and is sent in periods within at least 0.1 seconds. The PCR time stamp is incorporated into the transport stream packet to send the PCR.
The PCR is a total of 42 bits comprised of a 9-bit program clock reference extension, and a 33-bit program clock reference base. The program clock reference extension counts from 0 to 299, and the program clock reference base is incremented by one bit on the program clock extension carrier. The MPEG-2 system clock operates at 27 MHz so that a 24-hour portion of time is counted as a 27 MHz clock unit on this 42-bit counter. The PCR in other words, is a PCR counter value (PCR value) counted by the system clock.
Three documents relating to this invention are listed below.
(1) M. Perkins and P. Skelly, “A Hardware MPEG Clock Recovery Experiment in the Presence of ATM Jitter”, ATM Forum contribution to the SAA sub-workinggroup, 94-0434, May, 1994.
(2) G. Franceschini, “Extension of the Adaptive Clock Method to Variable Bit Rate Streams”, ATM Forum contribution to the SAA sub-working group, 94-0231, May, 1994.
(3) ISO/1EC13818-1(MPEG-2 Systems”, “GENERIC CODING OF MOVING PICTURES AND ASSOCIATED AUDIO”, Recommendation H.222.0, ISO/IEC JTC/SC29/G11NO721 rev, June 1984.
The above document (1) discloses hardware for achieving synchronization with the system clock of the information generator source, based on data simulating the jitter occurring on the ATM. The above document (2) discloses methods for synchronization relating to variable bit rates but does not discuss how to reduce delay distortion. The above document (3) is a draft of international standards relating to MPEG-2 system.
However, when the time stamp added by the encoder sent from the information generator source arrives at precisely the same period at the decoder, the decoder can easily synchronize with the encoder system clock by using the above disclosed methods. However, these methods assume as a necessary precondition that there is a fixed delay along the transmission path. The contents of the above document (3) in fact mention a fixed delay on the transmit path. Therefore, the following problems occur when a random delay such as on a network or namely, delay distortion is added, and there is also no means for rewriting the time stamp value to cope with a corresponding amount of delay distortion.
The time stamp value input to the PLL (Phase Locked Loop) frequency demodulator (hereafter called PLL) on the decoder side, has been added with the delay distortion, and the information source generator and decoder clock frequency differential. The PLL low-pass filter is designed to absorb the delay distortion however when the delay distortion cannot be adequately absorbed when large. Further problems are that long time is required for synchronizing when alleviating delay distortion in a PLL and the PLL circuit itself requires a complex d
Itakura Eisaburo
Okamori Atsushi
Sam Phirin
Sonnenschein Nath & Rosenthal LLP
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