Communications controller utilizing an external buffer memory wi

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395250, 2642285, 264239, 2642397, G06F 1300

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active

054349761

ABSTRACT:
A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.

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"VLSI Architecture For IEEE802.5 Token-Ring Lan Controller" by Tanaka Koichi, et al.; IEEE 1989 Custom Integrated Circuits Conference, published by IEEE, 1989.
"16-Mbit/s Adapter Chip for the IBM Token-Ring Local Area Network" by Jack Blair, et al., published by IEEE, vol. 24, No. 6., Dec. 1989.
"Token Ring", Local and Metropolitan Area Networks: Description of ISO/IEC 8802-5: 1992; IEEE Standard 802:5, pp. 25-40, p. 85.

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