Communication test circuit, communication interface circuit,...

Details Communication test circuit, communication interface circuit,... Communication test circuit, communication interface circuit,...

2011-08-09

2011-08-09

Ha, Dac (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S371000

Reexamination Certificate

active

07995646

ABSTRACT:
A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.

REFERENCES:
patent: 5515404 (1996-05-01), Pearce
patent: 7158899 (2007-01-01), Sunter et al.
patent: 2004/0120392 (2004-06-01), Searles et al.
Patent Abstracts of Japan: Publication No. 2005-004653, Date of Publication: Jan. 6, 2005.
Patent Abstracts of Japan: Publication No. 2002-314516, Date of Publication: Oct. 25, 2002.

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