Communication system for electronic equipment including distribu

Multiplex communications – Channel assignment techniques – Polling

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370458, H04J 1228

Patent

active

056848030

ABSTRACT:
A communication system interconnecting n slave processors (P1, P2, . . . , Pn) and a master processor (Pn+1) includes a first data communication bus, a second serial signalling bus, which acts as a conduit for a synchronous signalling frame, which consists of time intervals (IT) assigned to the processors, and circuitry for synchronizing the time intervals in the processors. In addition, n first comparing circuits, each associated with one of the slave processors, are provided for detecting the cyclic appearance of the IT assigned thereto. A second comparing circuit associated with the master processor indicates the cyclic appearance of a respective IT.

REFERENCES:
patent: 5379290 (1995-01-01), Kleijne
"Teleinformatique Transport et Traitement de l'Information Dans les Reseaux et Systemes Teleinformatiques" C. Macchi et al, pp. 206-218.
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