Communication system and communication control method

Details Communication system and communication control method Communication system and communication control method

1999-02-22

2003-04-29

Nguyen, Steven (Department: 2668)

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

C375S242000, C375S371000, C341S095000, C370S421000

Reexamination Certificate

active

06556583

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a communication system and a communication control method, wherein stations are connected to buses and communicate with each other through the buses.
2. Description of the Prior Art
A computing system is typically divided into CPU (central processing unit) sections, storage unit sections, input/output interface sections, etc, and a plurality of printed wire boards comprising the sections are installed in such system. The printed wire boards are interconnected by connecting connectors attached to the boards through a bus. A board provided with connectors and a bus is generally called a backplane. A communication system is built using a back-plane to enable printed wire boards in the system to communicate with each other. The prior art and its problems found in a communication system where backplanes are adopted, are as follows:
In a communication system comprising a master station and a slave station with a bus interconnecting the stations is often duplicated in order to increase communication reliability. In such a dual redundant bus system, two redundant buses are used alternately as long as both buses are in normal condition. If one of the buses should fail , the other normal bus is used to continue communication. Meanwhile, concurrent communication is carried out in order to check periodically whether or not the failed bus has recovered.
Another problem is that the master-slave communication does not take place unless a processor in the master station is aware of the statue of the redundant buses. More specifically, the processor must be aware of which of the two redundant buses is the active bus or the standby bus.
A further problem is that control must be carried out to switch from one bus to the other bus when either of the buses fails. A further problem is that the integrity of the transferred data is checked by adding check bits to the data. Although this checking procedure using check bits can examine the integrity of the data on the bus, it cannot examine the integrity of the data in areas other than the bus, such as bus interfaces, bridges, and repeaters.
Also, in communication systems, there are various reasons why the waveform of a bus signal may become distorted, as described below.
FIG. 1
shows a conventional communication system wherein a plurality of units
21
to
2
n are connected to a bus
1
in a multidrop configuration. Units
21
to
2
n communicate with each other through bus
1
.
FIG. 2
shows an equivalent circuit of bus
1
, wherein bus
1
has its own inductance L and stray capacitance C. When any of the units
21
-
2
n is connected to bus
1
, the circuit impedance decreases because of the capacitance component C of the unit itself. Accordingly, a signal transferred through bus
1
to the unit
21
. . .
2
n is reflected back to points where other units
21
. . .
2
n are connected. For example, if a signal is sent from unit
21
to unit
22
in
FIG. 1
, reflected signals occur at the connection points of units
22
to
2
n to bus
1
.
FIG. 3
shows the waveform of a signal at point B of FIG.
1
. Signal reflected by units
23
to
2
n reach point B before the signal received by unit
22
changes from a high level state to a low level state. As a result, the reflected signals from units
23
to
2
n are superposed with the received signal, as shown in
FIG. 3
, thus increasing the degree of waveform distortion. This may cause receiving unit
22
to malfunction. In the example of
FIG. 3
, the magnitude of the superposed reflected signals exceeds the low level threshold.
In order-to avoid this problem, the following restrictions are applied in the prior art: (A) Special devices having low capacitances are used with the units. (B) The number of connected units is reduced. It is desired to control the effects of such reflected signals without being limited by these prior art restrictions.
The waveform of a bus signal may also become distorted in the following manner. In a communication system, the transmitter circuit of a unit is provided with a driver IC (integrated circuit) that sends out signals to a bus. If any one bit, among a plurality of bits inputted to the driver IC, is kept static and all of the other bits are switched at the same time, the ground potential of the driver IC increases. This phenomenon is known as “ground bounce”, and noise may be induced at the static bit due to the effects of “ground bounce”. This noise is also known as “simultaneous switching noise”, and faulty data may be transferred due to the “simultaneous switching noise”. Once the “ground bounce” occurs, it takes some time for the ground potential to return to zero. This results in a disadvantageous increase in the communication delay time. It is desirable to reduce the effects of “ground bounce” which plagues prior art systems and methods.
FIG. 4
shows a standard communication system which has another problem. In
FIG. 4
, a transmitter circuit
11
and a receiver circuit
12
are connected to a transmission line
10
which constitutes a bus. Data is transferred from transmitter circuit
11
to receiver circuit
12
through transmission line
10
. Transmitter circuit
11
and receiver circuit
12
operate on asynchronous clocks having different phases. Before any signal transfer can be carried out in the communication system, data transmitted using the clock in the transmitter circuit must be somehow synchronized with the clock in the receiver circuit. There are certain difficulties existing as a result.
If data needs to be transferred using start stop synchronization that transmits data only, this synchronization is achieved only by using a clock which is faster than the data transfer rate for the receiver to sample the data. Normally, a high speed clock having a frequency which is approximately 16 times the data transfer rate is used.
On the other hand, if data needs to be transferred using clock synchronization that sends data together with a clock signal, this synchronization is achieved by writing the data once into a FIFO circuit in the receiver circuit using the transmitted clock signal, and then reading the data from the FIFO circuit using the clock in the receiver circuit.
Disadvantageously, data transfer based on start stop synchronization requires that the receiver circuit be provided with a clock that operates at speeds higher than the data transmission rate. As a result data transmission rate must be lower than the frequency of the clock available for the receiver circuit. For this reason, in the prior art, high speed signal transfer has been difficult to achieve.
Also, disadvantageously, data transfer based on clock synchronization requires that the data be written once into a FIFO circuit in the receiver circuit using the transmitted clock signal. For this reason, faulty data may be written into the FIFO circuit if the waveform of a received clock signal is distorted. The waveform of signals that propagate between circuits connected to the transmission line or bus are distorted due to the capacitive load of the transmission line or due to the effects of the noise that enters the transmission line. Thus, in the prior art, it is difficult to achieve high speed, consistent signal transfer.
Moreover, in the art, where two or more bus masters share the same system resources, such as storage units, through a common bus, concurrent or simultaneous requests from the respective bus masters to use the same bus cause conflicting demands. If this happens, some method of control must be used to decide which bus master should get first use of the bus. Bus arbitration is carried out for this purpose.
FIG. 5
shows a conventional communication system, wherein bus masters
31
to
3
n are connected to a data bus
42
and an arbitration bus
43
. A slave
44
is, for example, a storage unit and is connected to the data bus
42
. An arbiter
45
is incorporated in each of the bus masters
31
to
3
n. The arbiter
45
, after having executed arbitration procedure using arbitration bus
43
,

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