Communication processor having buffer list modifier control...

Details Communication processor having buffer list modifier control... Communication processor having buffer list modifier control...

1997-09-24

2001-10-16

Geckil, Mehmet B. (Department: 2152)

Electrical computers and digital processing systems: multicomput

Computer-to-computer protocol implementing

Computer-to-computer data framing

C370S276000

Reexamination Certificate

active

06304910

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to devices for transferring data in computer networks, and more particularly to a device utilizing control bits to facilitate generating and transmitting frames of data across a computer network boundary.
2. Description of Related Art
The number of computers and peripherals has mushroomed in recent years. This has created a need for improved methods of interconnecting these devices. A wide variety of networking paradigms have been developed to enable different kinds of computers and peripheral components to communicate with each other.
There exists a bottleneck in the speed with which data can be exchanged along such networks. This is not surprising because increases in network architecture speeds have not kept pace with faster computer processing speeds. The processing power of computer chips has historically doubled about every 18 months, creating increasingly powerful machines and bandwidth hungry applications. It has been estimated that one megabit per second of input/output is generally required per “MIPS” (millions of instructions per second) of processing power. With CPUs now easily exceeding 200 MIPs, it is difficult for network architecture to keep up with these faster speeds.
Area-wide networks (e.g., LANs and WANs) and channels are two approaches that have been developed for computer network architectures. Traditional networks offer a great deal of flexibility and relatively long distance capabilities. Channels, such as Enterprise System Connection (ESCON) and Small Computer System Interface (SCSI), have been developed for high performance and high reliability. Channels typically use dedicated short-distance connections between computers or between computers and peripherals.
Features of both channels and networks have been incorporated into a new network standard known as “Fibre Channel”. Fibre Channel systems combine the speed and reliability of channels with the flexibility and connectivity of networks. Fibre Channel products currently can run at very high data rates, such as 266 or 1062 Mbps. These speeds are sufficient to handle quite demanding applications such as uncompressed, full motion, high-quality video.
There are generally three ways to deploy Fibre Channel: simple point-to-point connections; arbitrated loops; and switched fabrics. The simplest topology is the point-to-point configuration, which simply connects any two Fibre Channel systems directly. Arbitrated loops are Fibre Channel ring connections that provide shared access to bandwidth via arbitration. Switched Fibre Channel networks, called “fabrics”, yield the highest performance by leveraging the benefits of cross-point switching.
The Fibre Channel fabric works something like a traditional phone system. The fabric can connect varied devices such as work stations, PCs, servers, routers, main frames, and storage devices that have Fibre Channel interface ports. Each such device can have an origination port that “calls” the fabric by entering the address of a destination port in a frame header. The Fibre Channel specification defines the structure of this frame. (This frame structure raises data transfer issues that will be discussed below and addressed by the present invention). The Fibre Channel fabric does all the work of setting up the desired connection, hence the frame originator does not need to be concerned with complex routing algorithms. There are no complicated permanent virtual circuits (PVCs) to set up. Fibre Channel fabrics can handle more than 16 million addresses, and so are capable of accommodating very large networks. The fabric can be enlarged by simply adding ports. The aggregate data rate of a fully configured Fibre Channel network can be in the tera-bit-per-second range.
Each of the three basic types of Fibre Channel connections are shown in
FIG. 1
, which shows a number of ways of using Fibre Channel technology. In particular, point-to-point connections
10
are shown connecting mainframes to each other. A Fibre Channel arbitrated loop
11
is shown connecting disk storage units. A Fibre Channel switch fabric
12
connects work stations
13
, mainframes
14
, servers
15
, disk drives
16
and local area networks (LANS)
17
. The LANS include, for example, Ethernet, Token Ring and FDDI networks.
An ANSI specification (X3.230-1994) defines the Fibre Channel network. The specification distributes Fibre Channel functions among five layers. As shown in
FIG. 2
, the five functional layers of the Fibre Channel are: FC-
0
-the physical media layer; FC-
1
-the coding and decoding layer; FC-
2
-the actual transport mechanism, including the framing protocol and flow control between nodes; FC-
3
- the common services layer; and FC-
4
-the upper layer protocol.
While the Fibre Channel operates at relatively high speed, it would be desirable to increase speeds further to meet the needs of faster processors. One way to do this would be to eliminate, or reduce, delays that occur at interface points. One such delay occurs during the transfer of a frame from the FC-
1
layer to the FC-
2
layer. At this interface, devices linked by a Fibre Channel data link receive Fibre Channel frames serially. A protocol engine receives these frames and processes them at the next layer, the FC-
2
layer shown in FIG.
2
. The functions of the protocol engine includes validating each frame; queuing up DMA operations to transfer each frame to the host; and building transmit frames.
The high bit speeds of the Fibre Channel data link places extreme demands on the protocol engine. Hence, some protocol engines can only operate in half-duplex mode, which means that the protocol engine can process data in only one direction at a time. This significantly slows down speed of the data transfer since either the transmit or the receive task must wait while the other task is performed.
Full-duplex protocol engines can process both received and transmitted frames simultaneously. Hence full-duplex protocol engines significantly improve data throughput. However, in full-duplex protocol engines, usually a microprocessor with local RAM handles the transmit and receive operations. The use of a microprocessor for this function greatly increases the cost of the protocol engine.
Conventional protocol engines also sometimes rely on the involvement of a host CPU on a frame-by-frame basis. For example, validation of received frames and generation of acknowledgments to received frames typically involve the host CPU. Involving the host CPU limits frame transmission and reception rates and prevents the host CPU from performing other tasks.
Moreover, a transmit protocol engine must have advance notice of the frame payload data size in order to build a transmit frame “header”. One way to accomplish this is for the transmit protocol engine to access computer memory where a series of frames have been stored and modify the header field in the last frame. However, if the transmit protocol engine cannot determine whether or not the current frame is the final frame before transferring payload data, this extra step slows the process of building and transmitting the frame header, and hence slows the overall communication data rate.
In view of the foregoing, objects of the invention include: increasing data transfer processing speeds in high speed networks such as the Fibre Channel network; providing a technique that can speed up a protocol engine's processing of data frames; providing a protocol engine that can perform high speed full duplex processing of data without involving the host CPU on a frame-by-frame basis; and providing a way for a transmit protocol engine to predetermine whether or not the current frame is the final frame, as well as having advance notice of the frame payload data size.
SUMMARY OF THE INVENTION
The invention is directed to the processing and transferring of frames of data in a computer data link. The invention is a full-duplex communication processor that uses dual micro-coded engines and specialized hardware to build transmit frames a

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