Communication processor for a packet-switched network

Details Communication processor for a packet-switched network Communication processor for a packet-switched network

1988-04-01

1990-12-18

Zache, Raulfe B.

Boots, shoes, and leggings

3642283, 3642222, 3642426, 3642428, G06F 100

Patent

active

049791001

ABSTRACT:
A packet switch receives data and processes it for assembly into packages. A bus allows communication between each of the data processing units of the switch and one or more storage units for storing the data packets. Arbitration for deciding which of the processing units will be granted access to the bus is performed by a system which selectively and alterably designates any of at least two different levels of priority of access to the bus for each of the processing units, and the relative percentages of time of access for the different priorty levels. The system assures greater access to the bus by those of the processing units having the higher level of priority. If communication is provided by two buses, the requests for access are alternated between them. The arbitration system provides selective access to the bus in any of a plurality of bus cycles including a read cycle, a write cycle and a read/modify/write cycle, and grants a request for access from a higher priority processing unit within one bus cycle.

REFERENCES:
patent: 4593282 (1986-06-01), Acampora et al.
patent: 4608685 (1986-08-01), Jain et al.
patent: 4651316 (1987-03-01), Kocan et al.
patent: 4654655 (1987-03-01), Kowalski
patent: 4654845 (1987-03-01), Mukerji
patent: 4807116 (1989-02-01), Katzman et al.

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