Multiplex communications – Fault recovery – Bypass an inoperative station
Reexamination Certificate
1998-07-07
2002-05-21
Hsu, Alpus H. (Department: 2662)
Multiplex communications
Fault recovery
Bypass an inoperative station
C370S248000, C370S403000, C370S424000, C709S251000
Reexamination Certificate
active
06392991
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication network and its control method and, more particularly, to a network system which has a node apparatus that can connect a plurality of terminal devices, and parallel multiplex transmission paths for connecting a plurality of node apparatuses.
2. Description of the Related Art
In recent years, as the information volume increases, a network that connects node apparatuses via parallel multiplex transmission paths is being examined to realize a high-speed, large-capacity network which connects terminal devices. For example, examples of the arrangement of such system are described in Japanese Laid-Open Patent Nos. 8-172394 and 8-237306.
In a node apparatus described in Japanese Laid-Open Patent Nos. 8-172394 and 8-237306, one terminal device is connected to each of eight parallel multiplex transmission paths (eight channels), and a packet transmitted from a certain terminal device is output to the channel to which that terminal device is connected in the node apparatus and is then input to an switch fabric of the node apparatus.
The packet is inserted into another channel in the switch fabric, and is then output to a neighboring node apparatus.
The switch fabric used in the node apparatus has eight input terminals and eight output terminals, and sequentially connects these input and output terminals according to specific patterns so as to prevent the input terminals from being connected to a single output terminal in an identical time band, thus switching the channels (see Japanese Laid-Open Patent Nos. 8-172394 and 8-237306 for more).
When communications are made between such node apparatuses, since a terminal device is connected to a given channel, an upstream neighboring node apparatus of the node apparatus to which the destination terminal device of a packet is connected transmits the packet onto the channel to which the destination terminal device is connected.
However, in the above-mentioned prior art, if the destination terminal device of the packet transmitted from a given terminal device is connected to a downstream neighboring node apparatus of the node apparatus to which the source terminal device is connected, the communication band narrows as compared to a case wherein the packet is transmitted to a terminal device connected to another node apparatus.
More specifically, when a packet is transmitted to a terminal device other than that connected to the downstream neighboring node apparatus of the node apparatus to which the source terminal device is connected, the node apparatus to which the source terminal device is connected can transmit that packet using an arbitrary one of a plurality of channels. However, when the packet is transmitted to a terminal device connected to the downstream neighboring node apparatus, the node apparatus must transmit the packet using only the channel to which the destination terminal device is connected.
Hence, in the above-mentioned prior art, communications can be made even when the node apparatus to which the destination terminal device neighbors on the downstream side of the node apparatus to which the source terminal device is connected, but the communication band narrows as compared to a case wherein the node apparatus to which the destination terminal device is connected does not neighbor on the downstream side of the node apparatus to which the source terminal device is connected.
A reference example that partially quotes the arrangement of Japanese Laid-Open Patent No. 8-237306 will be described below to explain the prior art in more detail.
FIG. 5
is a diagram showing the arrangement of a node apparatus in a network of the reference example, and exemplifies an arrangement in which terminals
551
to
558
are connected to a node apparatus
500
via sub transmission paths. Reference numerals
501
to
508
denote separation/insertion units serving as separation/insertion means. Each separation/insertion unit has a function of detecting the addresses of packets input from the corresponding parallel multiplex transmission path, separating them into those to be transmitted to the terminal and those to be input to a buffer, and inserting a packet transmitted from the terminal into a packet flow input form the parallel multiplex transmission path. Reference numerals
511
to
518
denote buffers serving as buffer means each having a function of temporarily storing a packet output from the corresponding separation/insertion unit in a storage area corresponding to the output terminal of a switch
541
. Reference numerals
521
to
528
and
531
to
538
denote parallel multiplex transmission paths as a plurality of parallel channels to connect neighboring nodes. These transmission paths are realized by, e.g., a plurality of space division multiplexing optical fiber transmission paths, or wavelength multiplex transmission paths which are wavelength-divided and multiplexed on a single optical fiber. Reference numeral
541
denotes a switch, which is controlled by a switch controller
542
to connect packets input to its input terminals IN
1
to IN
8
to arbitrary output terminals OUT
1
to OUT
8
. The switch
541
attains switching using a space division switch or the like when a plurality of optical fiber transmission paths are used as the parallel multiplex transmission paths. On the other hand, when wavelength multiplex transmission paths are used, the switch
541
between neighboring nodes is constructed by connecting a transmitter comprising a plurality of variable wavelength laser diodes and a wavelength multiplexer to the wavelength multiplex transmission paths, and separating the respective wavelengths using a wavelength demultiplexer in a receiver of the wavelength multiplex transmission paths, and switches by setting the transmission wavelengths of the variable wavelength laser diodes at arbitrary wavelengths &lgr;
1
to &lgr;
8
. Reference numeral
542
denotes a switch controller which controls the switch according to control patterns shown in, e.g., FIG.
4
. Reference numeral
543
denotes a buffer controller which controls the buffers to read out the stored packets when the input terminals of the switch connected to the individual buffers are connected to desired output terminals.
FIG. 8
shows the internal arrangement of each of the separation/insertion units
501
to
508
. Reference numeral
801
denotes a header detector for detecting the destination address from a packet header;
802
and
803
, gates for outputting or intercepting the input signals;
804
, a selector for outputting one of the two input signals; and
805
, a FIFO (First In First Out) for temporarily storing a packet. In each of the separation/insertion units
501
to
508
, the header detector
801
detects the header of a packet input from the corresponding parallel multiplex transmission path, and the gates
802
and
803
are opened/closed depending on the header contents. The header detector
801
pre-stores the address of a terminal connected to that separation/insertion unit, and when the detected destination address matches the stored address, the gates
803
and
802
are respectively opened and closed to output that packet in only the terminal direction. When the detected destination address does not match the stored address, the gates
802
and
803
are respectively opened and closed to output that packet to only the selector, and the packet is sent to the buffer via the selector
804
. On the other hand, a packet transmitted from the terminal is temporarily stored in the FIFO
805
, and is read out therefrom when the packet flow input from the gate
802
to the selector
804
has a space. Then, the packet is sent to the buffer via the selector
804
.
FIG. 3
shows the internal arrangement of each of the buffers
511
to
518
. Reference numeral
301
denotes a buffer memory having storage areas
1
to
8
corresponding to the output terminals of the switch
541
;
302
, a header detector for detecting the destination address from a packe
Nakata Toru
Yamamoto Takahisa
Canon Kabushiki Kaisha
Hsu Alpus H.
Morgan & Finnegan L.L.P.
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