Pulse or digital communications – Systems using alternating or pulsating current – Plural channels for transmission of a single pulse train
Reexamination Certificate
1998-08-11
2003-06-03
Pham, Chi (Department: 2631)
Pulse or digital communications
Systems using alternating or pulsating current
Plural channels for transmission of a single pulse train
C375S316000, C375S295000
Reexamination Certificate
active
06574283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication method, a transmission apparatus, a reception apparatus, and a radio communication system, which are suitable for application to, for example, a cellular telephone system in which a mobile radio station radio-communicates with a base station that is a fixed radio station.
2. Description of the Related Art
In a conventional radio communication system, an area that is provided communication services is divided into cells of a desired size. A base station that acts as a fixed radio station is installed in the cell, and a cellular telephone that acts as a mobile radio station radio-communicates with the base station in the cell in which that cellular telephone is present. Various methods for communication between a cellular telephone and a base station have been proposed, and a representative one is a Time Division Multiple Access method referred to as TDMA method.
For example, as shown in
FIG. 1A
, the TDMA method temporally divides a predetermined frequency channel into frames F
0
, F
1
, . . . of a predetermined time interval while dividing each frame into time slots TS
0
to TS
3
of a predetermined time interval, and uses this frequency channel to transmit a transmission signal at the timing of the time slot TS
0
that is assigned to the station itself. This method enables a plurality of communications to use the same frequency channel (so-called multi-communication), thereby enabling frequencies to be efficiently used. In FIG.
1
B and the subsequent drawings, the time slot TS
0
assigned for transmission is called a “transmission slot TX”, and data blocks sent by a single transmission slot TX is called a “slot”.
Transmission and a reception apparatuses for a radio communication system that transmits and receives a digital signal using the TDMA method are described with reference to
FIGS. 2 and 3
. The transmission and reception apparatuses shown in
FIGS. 2 and 3
are mounted in a cellular telephone and a base station in a cellular telephone system, for example, and are used for communications between them.
As shown in
FIG. 2A
, a transmission apparatus
1
is roughly composed of a convolution coding circuit
2
, an interleave buffer
3
, a slotting circuit
4
, a Differential Quadrature Phase Shift Keying (DQPSK) modulation circuit
5
, a transmission circuit
6
, and an antenna
7
, wherein transmission data S
1
to be transmitted is first input to the convolution coding circuit
2
.
The convolution coding circuit
2
consists of a predetermined number of shift registers and a predetermined number of exclusive OR circuits, and convolution-codes the input transmission data S
1
to output the resulting transmission symbols S
2
to the interleave buffer
3
. The interleave buffer
3
sequentially stores the transmission symbols S
2
in its internal storage. Once the entire storage has been filled with the transmission symbols S
2
(a desired amount of transmission symbols S
2
have been stored), the buffer
3
randomly changes the order of the transmission symbols S
2
(hereafter such a change of order is referred to as “interleaving”). The resulting transmission symbols S
3
are output to the slotting circuit
4
. The interleave buffer
3
has a sufficient capacity to store a plurality of slots so that transmission symbols are distributed to a large number of transmission slots TX.
To assign the transmission symbols S
3
to the transmission slots TX, the slotting circuit
4
rearranges the transmission symbols S
3
in slots, and sequentially outputs the slotted transmission symbols S
4
to the DQPSK modulation circuit
5
. The DQPSK modulation circuit
5
DQPSK-modulates the transmission symbols S
4
supplied in slots to generate a transmission signal S
5
representing the symbol information as phase values, and outputs them to the transmission circuit
6
.
The transmission circuit
6
filters the transmission signal S
5
supplied in slots, converts it into an analog signal, and converts the frequency of said analog transmission signal to generate a transmission signal S
6
of a predetermined frequency channel. The transmission circuit
6
then amplifies the transmission signal S
6
up to a predetermined voltage and outputs said signal to the antenna
7
. Thus, the transmission apparatus
1
sends out the transmission signal S
6
that has been partitioned into slots, in synchronism with the timing of the transmission slots TX. For reference,
FIG. 2B
schematically shows the signal processing executed in each circuit of the transmission apparatus
1
described above.
On the other hand, as shown in
FIG. 3A
, a reception apparatus
10
is roughly composed of an antenna
11
, a reception circuit
12
, a DQPSK demodulation circuit
13
, a slot concatenation circuit
14
, a deinterleave buffer
15
, and a Viterbi decoding circuit
16
. The reception apparatus
10
uses the antenna
11
to receive the transmission signal S
6
sent from the transmission apparatus
1
, and outputs said signal to the reception circuit
12
as a reception signal S
11
. The reception circuit
12
amplifies the input reception signal S
11
, converts the frequency of the reception signal S
11
to obtain a baseband signal, and filters said baseband signal. The reception circuit
12
then converts the baseband signal into a digital one to obtain a reception signal S
12
that has been DQPSK-modulated, and outputs said signal to the DQPSK demodulation circuit
13
.
The DQPSK demodulation circuit
13
DQPSK-demodulates the reception signal S
12
to obtain symbol information, and outputs this information to the slot concatenation circuit
14
as reception symbols S
13
. The reception symbols S
13
are not a binary signal having a value of “0” or “1”, but a multi-value signal due to noise components added on the transmission path. The slot concatenation circuit
14
concatenates the reception symbols S
13
fragmentarily obtained in each slot so that said symbols form continuous signals. Once an amount of reception symbols S
13
have been accumulated up to the capacity of the subsequent deinterleave buffer
15
, the circuit
14
concatenates said reception symbols S
13
and outputs concatenated reception symbols S
14
to the deinterleave buffer
15
.
The deinterleave buffer
15
has a sufficient capacity to store a plurality of slots. Once the deinterleave buffer
15
has sequentially stored the supplied reception symbols S
14
, it uses the reverse procedure to that of the interleave buffer
3
on the transmission apparatus
1
in order to change the order of the reception symbols S
14
to the original one, and outputs the resultant reception symbols S
15
to the Viterbi decoding circuit
16
(hereafter, returning to the original order is referred to as “deinerleaving”). The Viterbi decoding circuit
16
consists of a soft-decision Viterbi decoding circuit. The circuit
16
assumes trellis codes for convolution based on the input reception symbols S
15
and selects from all possible data state transitions (so-called maximum likelihood sequence estimation) to recover reception data S
16
indicating the transmitted data for output. FIG.
3
B schematically shows the signal processing executed in each circuit of the reception apparatus
10
described above.
In the reception apparatus
10
, the Viterbi decoding circuit
16
executes the maximum likelihood sequence estimation to recover the reception data S
16
, but this estimation must be more accurate to more accurately recover the reception data S
16
.
This is specifically described below. As described above, the reception symbols S
13
output from the DQPSK demodulation circuit
13
constitute a multivalue signal. The value of the multi-value signal roughly indicates the reliability of the reception symbols. A Viterbi decoding circuit that decodes such a multi-value signal is called a softdecision Viterbi decoding circuit, and normally recovers data by means of the maximum likelihood sequence estimation taking the reliability of each symbol into considerati
Sakoda Kazuyuki
Suzuki Mitsuhiro
Burd Kevin M
Maioli Jay H.
Sony Corporation
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