Communication link interface with different clock rate tolerance

Details Communication link interface with different clock rate tolerance Communication link interface with different clock rate tolerance

1989-09-19

1991-05-28

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

371 471, H04L 700

Patent

active

050200810

ABSTRACT:
A communication link interface having an assembly register which is loaded in response to a transmitter's clock rate and unloaded in response to a receiver's clock connected to the interface. The assembly register holds a series of data words received from the communication link. Logic gates or flip flops are provided to insure a time delay between loading the assembly register and unloading it.

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