Communication controller using multiported random access memory

Details Communication controller using multiported random access memory Communication controller using multiported random access memory

1984-12-10

1986-08-05

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1312

Patent

active

046046836

ABSTRACT:
A communication controller for facilitating bidirectional digital data transfers between a host processor and various types of networks. The controller architecture is characterized by multiple independent data transfer buses coupled to a central multiple port random access memory. The architecture avoids microprocessor bus contention in favor of RAM contention and thus enhances aggregate system throughput. Moreover, the buses are capable of performing operations concurrently to thereby further enhance system throughput.

REFERENCES:
patent: 4075691 (1978-02-01), Davis et al.
patent: 4156907 (1979-05-01), Rawlings et al.
patent: 4377843 (1983-03-01), Garringer et al.
patent: 4399503 (1983-08-01), Hawley
patent: 4456957 (1984-06-01), Schieltz
patent: 4488231 (1984-12-01), Yu et al.

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