Multiplex communications – Diagnostic testing – Loopback
Reexamination Certificate
1997-04-04
2003-11-11
Kizou, Hassan (Department: 2662)
Multiplex communications
Diagnostic testing
Loopback
C370S395100
Reexamination Certificate
active
06646992
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a communication control method and an equipment for implementing the same, and more particularly to a communication control method inclusively having test function for testing (checking) the operation of the equipment (provided for communication control) at the physical layer in the ATM communication, and an equipment for implementing such a method.
In recent years, as a system in which high speed and large capacity data communication can be made, development in regard to the ATM communication is being carried out.
In the ATM communication, a series of data processing within the communication equipment are carried out in the state caused to be of hierarchical (layered) structure consisting of plural protocol (control procedure) layers. In this protocol hierarchical structure, the layer located at the lowest level is the physical layer.
In carrying out such ATM communication, conversion is carried out between the data form at the physical layer, i.e., the data form on the transmission line and the data form at the layer higher than the physical layer. The data form on the transmission line is the form of the frame in conformity with, e.g., SONET/SDH standard, etc. The layer which is higher than the physical layer by one is the ATM layer. The data form in this layer is ATM cell. The ATM cell is data packet having unit length of 53 bytes, and consists of header of 5 bytes in which destination of transmission, etc. is described and payload of 48 bytes in which user data is stored.
The outline of the configuration of a communication control equipment
300
in the physical layer related to this invention is shown in FIG.
1
. The communication control equipment
300
includes a receiving system assembled of circuits
305
~
308
, a transmitting system assembled of circuits
301
~
304
, a loop back circuit comprised of a selector
309
provided therebetween, and a host interface
310
for carrying out interface with the host CPU.
In the transmission system, when ATM cell is sent from an ATM layer control unit
400
, it is inputted to the transmission cell processing section
302
through the transmission cell interface
301
. In the transmission cell processing section
302
, after necessary processing is implemented to the header of the ATM cell, the ATM cell thus processed is transferred to the transmission frame assembling section
303
. In this case, for a time period during which no data cell is sent to the control equipment
300
of the physical layer (hereinafter referred to as physical layer control unit as occasion may demand) from the ATM layer control unit
400
, idle cell indicating that no data cell is sent is generated at the transmission cell processing section
302
, and the idle cell thus generated is transferred to the transmission frame assembling section
303
in place of the data cell.
At the transmission frame assembling section
303
, data cell or idle cell is converted from the data form of the ATM cell into the data form on the transmission line so that frame data is provided. Thereafter, this frame data is transferred from the transmission line interface
304
to the transmission line.
In the receiving system, frame data represented in the data form on the transmission line is inputted to the receiving frame disassembling section
306
through the receiving line interface
305
and via selector
309
of which detail will be described later. At the receiving frame disassembling section
306
, the frame data is disassembled into the portion where cells are stored thereof and the portion of frame management data except for the above. The portion of the frame management data is stored into memory, etc. provided within the receiving frame disassembling section
306
. On the other hand, the portion where cells are stored is transferred to the receiving cell processing section
307
. At the receiving cell processing section
307
, cell synchronization is implemented with respect to the portion where cells are stored so that boundaries between cells are caused to become clear. Thereafter, various processing corresponding to the header pattern are implemented thereto. The result of this processing is indicated at the status register provided within the host interface
310
. The cells extracted from the frame data in a manner as described above are outputted to the ATM layer control unit
400
through the receiving cell interface
308
.
Meanwhile, data cell or idle dell outputted from the transmission frame assembling section
303
is ordinarily transmitted to the transmission line interface
304
. However, in the case where test or check of the internal operation of the control unit
300
is carried out, output of the selector
309
is switched, thereby making it possible to allow the cell to undergo loop back to the receiving frame disassembling section
306
. As stated above, the selector
309
is provided for the purpose of test. Ordinarily, output of the receiving line interface
305
is delivered to the receiving frame disassembling section
306
.
At the time of test, output of the transmission frame assembling section
303
is delivered to the receiving frame disassembling section
306
, whereby data is sent from the transmission system to the receiving system. At the time of carrying out test, output of the selector
309
is initially switched to make such a setting that output of the transmission frame assembling section
303
is delivered to the receiving frame disassembling section
306
. Thus, test cell in the form of the ATM cell inputted from the ATM layer control unit
400
to the physical layer control unit
300
is converted into the form of the frame data at the transmission frame assembling section
303
. The frame data thus obtained is inputted to the receiving frame disassembling section
306
through the selector
309
. At the receiving frame disassembling section
306
, the frame data including the test cell therein is disassembled into the portion where cell is stored and the frame management data portion except for the above. Then, processing corresponding to the header pattern is carried out by the receiving cell processing section
307
. The processing result obtained at this time is monitored by the host computer through the host interface
310
. Thus, the host computer can survey or confirm whether or not the internal processing is normally carried out at the receiving cell processing section
307
. In this case, by rewriting, in dependency upon the test purpose, the header pattern of the test cell that the ATM layer control unit
400
delivers to the physical layer control unit
300
, tests can be made with respect to various functions. This rewrite operation of the header pattern is carried out by the host computer.
A Alternatively, there were instances where dedicated evaluation equipment is provided at the external in place of the ATM layer control unit
400
to generate test cells by using this equipment to carry out test.
Further, in the physical layer control unit
300
, it is also conceivable to input, without using the selector
309
, test cell in the form of frame data from the transmission line to the receiving line interface
305
to deliver it to the receiving frame disassembling section
306
and the receiving cell processing section
307
. However, also in this case, dedicated evaluation equipment is required. Eventually, the communication control equipment (unit) shown in
FIG. 1
requires dedicated evaluation equipment in all of the above-described cases. The reason thereof will be described in detail.
As an item of test carried out by inputting test cell to the physical layer control unit
300
in place of the communication data, there are tests of GFC (General Flow Control) function, bit error correction function of header, and cell counter function, etc. The GFC function is a function for carrying out operation to stop sending-out of transmit data in accordance with the content of the leading 4 bits of the header of the received cell, etc. The bit error correction fu
Hogan & Hartson LLP
Kizou Hassan
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