Multiplex communications – Wide area network – Packet switching
Patent
1990-06-18
1992-05-12
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 941, H04J 326
Patent
active
051133920
ABSTRACT:
In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory block.
REFERENCES:
patent: 5016248 (1991-05-01), Kudoh
IEEE, Journal on Selected Areas, vol. SAC-3, No. 6, 1985, "A Metropolitan Area Network", Daniel Sze, pp. 815-824.
"B486 MAC Bridge in 410 M6ps Multimedia Highway", K. Shikata et al., Drafts B-486 for a Spring National Meeting, 1989, of the Institute of Electronics, Information, and Communications Engineers of Japan.
Amada Eiichi
Hirayama Satoru
Iiyama Tatsuhito
Jusa Hidehiko
Kobayashi Naoya
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
Marcelo Melvin
Olms Douglas W.
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