Pulse or digital communications – Systems using alternating or pulsating current – Plural channels for transmission of a single pulse train
Reexamination Certificate
2000-01-21
2004-01-06
Phu, Phoung (Department: 2631)
Pulse or digital communications
Systems using alternating or pulsating current
Plural channels for transmission of a single pulse train
C714S792000
Reexamination Certificate
active
06674807
ABSTRACT:
PRIORITY
This application claims priority to an application entitled “Communication Apparatus And Method for CDMA Communication System” filed in the Korean Industrial Property Office on Jan. 21, 1999 and assigned Serial No.
99-2311
, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a channel coding apparatus and method for a Code Division Multiple Access (CDMA) communication system, and in particular, to a channel coding apparatus and method for a DS (Direct Sequence)-CDMA communication system. Further, the present invention provides a channel decoding apparatus and method for receiving signals transmitted from a base station having the above channel coding apparatus.
2. Description of the Related Art
Current CDMA communication systems are implemented according to the IS-95 standard. With an increase in the sophistication of CDMA communication technology and a decrease in usage costs, there has been exponential growth in the number of subscribers to CDMA communication services. Accordingly, many methods have been proposed for meeting subscribers' ever-increasing demands for high quality CDMA service. For example, several methods for improving the forward link structure in CDMA communication system have been proposed.
One such method for improving the forward link structure, especially the forward link fundamental channel designed for the third generation multicarrier CDMA system, was proposed in the TIA/EIA TR45.5 conference and approved on May 15, 1998 by the Telecommunications Industry Association (TIA). A forward link structure for a multicarrier CDMA communication system is illustrated in FIG.
1
.
With reference to
FIG. 1
, a channel encoder
10
encodes input data, and a rate matcher
20
repeats and punctures symbols outputted from the channel encoder
10
. Here, the data input to the channel encoder
10
has a variable bit rate. The rate matcher
20
repeats and punctures the coded data bits (i.e., symbols) outputted from the channel encoder
10
in order to match the symbol rates for variable bit rate data. A channel interleaver
30
interleaves an output of the rate matcher
20
. A block interleaver is typically used for the interleaver
30
.
A long code generator
91
generates a long code which uniquely identifies each subscriber. A decimator
92
decimates the long code to match the rate of the long code to the rate of the symbols outputted from the interleaver
30
. An adder
93
mixes an output of the channel interleaver
30
and an output of the decimator
92
. An exclusive OR gate is typically used for the adder
93
.
A demultiplexer
40
sequentially demultiplexes data outputted from the adder
93
to multiple carriers A, B and C. First to third signal converters
51
-
53
convert signal levels of binary data outputted from the demultiplexer
40
by converting input data of ‘0’ to ‘+1’ and input data of ‘1’ to −‘1’. First to third Walsh encoders (or orthogonal modulators)
61
-
63
encode data outputted from the first to third signal converters
51
-
53
, respectively, using corresponding Walsh codes. Here, the Walsh codes have a length of 256 bits. First to third modulators
71
-
73
modulate outputs of the first to third Walsh encoders
61
-
63
, respectively. Here, QPSK (Quadrature Phase Shift Keying) spreaders can be used for the modulators
71
-
73
. First to third attenuators (or gain controllers)
81
-
83
control gains of the modulated signals outputted from the first to third modulators
71
-
73
according to corresponding attenuation signals GA-GC, respectively. Here, the signals are outputted from the first to third attenuators
81
-
83
with different carriers A, B and C.
In the forward link structure of
FIG. 1
, the channel encoder
10
, having a coding rate of R=1/3, encodes a single input data bit into 3 coded data bits (i.e., code words or symbols). Such coded data bits are demultiplexed to the three carriers A, B and C after rate matching and channel interleaving. That is, the multicarrier CDMA forward link of
FIG. 1
encodes and interleaves the input data and then demultiplexes the data to the three carriers before transmission.
FIG. 1
shows a multicarrier CDMA communication system. This can be modified to a single-carrier CDMA communication system by removing the demultiplexer
40
and using a signal converter, an orthogonal modulator, a spreader and an attenuator for single carrier.
FIG. 2
is a detailed diagram illustrating the channel encoder
10
, the rate matcher
20
and the channel interleaver
30
. In
FIG. 2
, data at the first rate is composed of 172 bits (full rate) per 20 ms frame; data at the second rate is composed of 80 bits (1/2 rate) per 20 ms frame; data at the third rate is composed of 40 bits (1/4 rate) per 20 ms frame; and data at the fourth rate is composed of 16 bits (1/8 rate) per 20 ms frame.
First to fourth CRC (Cyclic Redundancy Code or Cyclic Redundancy Check) generators
111
-
114
generate CRC bits corresponding to the respective input data having different rates and add the generated CRC bits to the input data. Specifically, a 12-bit CRC is added to the 172-bit data of the first rate; an 8-bit CRC is added to the 80-bit data of the second rate; a 6-bit CRC is added to the 40-bit data of the third rate; and a 6-bit CRC is added to the 16-bit data of the fourth rate. First to fourth tail bit generators
121
-
124
add 8 tail bits to the CRC-added data, respectively. Therefore, the first tail bit generator
121
outputs 192 bits; the second tail bit generator
122
outputs 96 bits; the third tail bit generator
123
outputs 54 bits; and the fourth tail bit generator
124
outputs 30 bits.
First to fourth encoders
11
-
14
encode data output from the first to fourth tail bit generators
121
-
124
, respectively. A convolutional encoder having a constraint length of K=9 and a coding rate of R=1/3 can be used for the encoders
11
-
14
. In this case, the first encoder
11
encodes the 192-bit data output from the first tail bit generator
121
into 576 symbols at the full rate; the second encoder
12
encodes the 96-bit data output from the second tail bit generator
122
into 288 symbols at 1/2 rate; the third encoder
13
encodes the 54-bit data output from the third tail bit generator
123
into 162 symbols at about 1/4 rate; and the fourth encoder
14
encodes the 30-bit data output from the fourth tail bit generator
124
into 90 symbols at about 1/8 rate.
The rate matcher
20
includes repeaters
22
-
24
and symbol deletion devices
27
-
28
. The repeaters
22
-
24
repeat symbols outputted from the second to fourth encoders
12
-
14
at predetermined times in order to increase output symbol rates to the full rate of 576 symbols (or bits). For instance, since the second encoder
12
outputs 288 symbols (=1/2 the 576 symbols outputted from the first encoder
11
), the second repeater
22
repeats the received 288 symbols two times to output 576 symbols. The “second repeater” means that it is the repeater for the second rate (1/2 rate); there is no first repeater. The same numbering system is used for the symbol deletion devices. The symbol deletion devices
27
and
28
delete extra symbols outputted from the repeaters
23
and
24
in order to match the number of symbols at the full rate (i.e., 576). For instance, since the third encoder
13
outputs 162 symbols (>1/4 the 576 symbols outputted from the first encoder
11
), the third repeater
23
repeats the received 162 symbols four times to output 648 symbols which exceeds the full rate of 576 symbols. In order to match the symbol rate to the full rate, the third symbol deletion device
27
deletes every ninth symbol of the 648 symbols to output the full rate of 576 symbols. In addition, since the fourth encoder
14
outputs 90 symbols (>1/8 the 576 symbols output from the first encoder
11
), the fourth repeater
24
repeats the received 90 symbols eight times to output 720 symbols which exceed
Kang Hee-Won
Kim Jae-Yoel
Kong Jun-Jin
No Jong-Seon
Park Chang-Soo
Dilworth & Barrese LLP
Phu Phoung
LandOfFree
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