Communicating instructions and data between a processor and...

Details Communicating instructions and data between a processor and... Communicating instructions and data between a processor and...

2011-01-11

2011-01-11

Moe, Aung S (Department: 2474)

Multiplex communications

Communication techniques for information carried in plural...

C710S005000, C710S039000, C712S225000

Reexamination Certificate

active

07869459

ABSTRACT:
A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

REFERENCES:
patent: 5870627 (1999-02-01), O'Toole et al.
patent: 6363438 (2002-03-01), Williams et al.
patent: 6453365 (2002-09-01), Habot
patent: 6496925 (2002-12-01), Rodgers et al.
patent: 6662242 (2003-12-01), Holm et al.
patent: 7010626 (2006-03-01), Kahle
patent: 7111089 (2006-09-01), Karam et al.
patent: 7386636 (2008-06-01), Day et al.
patent: 7500039 (2009-03-01), Day et al.
patent: 2003/0099254 (2003-05-01), Richter
patent: 2004/0158664 (2004-08-01), Zilavy
patent: 2004/0193754 (2004-09-01), Kahle
patent: 2004/0264445 (2004-12-01), Day et al.
patent: 2006/0010264 (2006-01-01), Rader et al.
patent: 2006/0059302 (2006-03-01), Tsuruta
patent: 2007/0041403 (2007-02-01), Day et al.
patent: 2007/0043936 (2007-02-01), Day et al.
patent: 2007/0079018 (2007-04-01), Day et al.
patent: 2008/0244200 (2008-10-01), Day et al.
patent: 1 026 596 (2000-08-01), None
patent: PUPA S62 280956 (1987-05-01), None
patent: PUPA H01-048166 (1989-02-01), None
patent: 2000-267987 (2000-09-01), None
patent: PUPA 02-342165 (2002-11-01), None
patent: PUPA 2005-056401 (2005-03-01), None
patent: WO/0196979 (2001-12-01), None
USPTO U.S. Appl. No. 11/207,970, 2 pages.
USPTO U.S. Appl. No. 11/207,971, 2 pages.
USPTO U.S. Appl. No. 11/207,986, 2 pages.
USPTO U.S. Appl. No. 12/106,483, 2 pages.
USPTO U.S. Appl. No. 12/361,907, 2 pages.
Notice of Allowance mailed Apr. 7, 2010 for U.S. Appl. No. 11/207,970; 4 pages.
Office Action mailed Jun. 14, 2010 for U.S. Appl. No. 12/361,907; 9 pages.
Response to Office Action filed with the USPTO on Mar. 30, 2010 for U.S. Appl. No. 12/361,907; 14 pages.
Response to Office Action filed with the USPTO on Sep. 13, 2010 for U.S. Appl. No. 12/361,907; 16 pages.

Affiliated with

Also associated with

Rating

Communicating instructions and data between a processor and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Communicating instructions and data between a processor and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Communicating instructions and data between a processor and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2650162