Commonly housed diverse semiconductor die

Details Commonly housed diverse semiconductor die Commonly housed diverse semiconductor die

2000-08-24

2001-10-02

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S497000, C257S773000, C257S901000

Reexamination Certificate

active

06297552

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more specifically relates to a novel device in which a plurality of die, which may be of diverse size and of diverse junction pattern, are fixed to a common lead frame and within a common package or housing.
BACKGROUND OF THE INVENTION
Numerous electrical circuits, for example, DC to DC converters, synchronous converters, and the like require a number of semiconductor components such as MOSFETs and Schottky diodes. These components are frequently used in portable electronics apparatus and are commonly separately housed and must be individually mounted on a support board. The separately housed parts take up board space. Further, each part generates heat and, if near other components, such as microprocessors, can interfere with the operation of the microprocessor.
It would be desirable to reduce the board space required by plural semiconductor devices and to reduce part count and assembly costs in power converters and other power subsystems for high-density applications.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, two or more diverse semiconductor die are laterally spaced and mounted on a common lead frame with a first one of each of their power terminals electrically connected to the lead frame. The main lead frame body then has a first set of externally available pins which are used to make connection to the first one of the power terminals of each of the diverse die. The die are also provided with second power terminals at the tops of the die, and these are connected to respective external pins of the lead frame which are isolated from one another and from the first set of external pins. One or more of the die may also contain a control terminal, such as the gate electrode of a MOSFET die, and a further and isolated pin of the lead frame is connected to this gate terminal.
The lead frame and die are then over-molded with a suitable insulation compound housing, with the various pins extending in-line and beyond the edge surfaces of the housing and available for external connection.
The housing may take the form of a surface-mounted housing with a very small “footprint”. By way of example, a MOSFET die and a Schottky diode die may be contained within and may have their drain electrodes and cathode electrodes respectively soldered to a common conduction lead frame pad to be interconnected within the housing. The FET source and gate terminals on top of the die are wire bonded to insulated lead frame pins and the top Schottky diode anode is also connected to an isolated pin so that any desired external connection can be made to the package.
While any package style can be used, the novel invention has been carried out with an SO-8 style small outline package.
The novel package of the invention can improve efficiency of a DC to DC converter by reducing power drain on batteries, leading to a longer life. For desk top systems, the device reduces power dissipation and heat generation near temperature-sensitive parts such as microprocessors. The device also provides substantial savings in board space while reducing component count and assembly costs.
For example, the use of a copackaged FET Type IRF7422D2 (a (−20) volt 90 mohm P channel FET) and a Schottky diode (30 volt, 1 ampere) in a buck converter circuit provided a 60% saving in board space and assembly cost.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.


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“Electronic Engineering”, Dec. 1991, Yehya Kasem and Leo Feinstein,High Performance Power Packagage for Power IC Devices, Part 1, pp. 35-43.

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