Common source EEPROM and flash memory

Details Common source EEPROM and flash memory Common source EEPROM and flash memory

2001-10-30

2003-08-12

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

C365S185050, C365S185330

Reexamination Certificate

active

06606265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor nonvolatile memories. More particularly, the present invention relates to an improved EEPROM and flash memories.
2. The Prior Art
Several types of nonvolatile memory cells have been used in commercial products for many years, ranging from EPROM to EEPROM and Flash memories. See, for example, “IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays” IEEE Std 1005-1998. The cited reference provides a good background of the various types of memory devices that have been produced and provide a list of the terms used in this disclosure.
EPROM and Flash memories usually employ a single MOS transistor with two gates stacked on top of each other, the floating gate and the control gate, and the conductive state of the transistor can be changed by injecting electrons onto or removing electrons from the floating gate. EEPROM (byte erasable) memories usually are fabricated with separate select and control gate (such as the FLOTOX cell), although there are examples of products where a split gate is also used.
The majority of the memory cells either of the stacked or split gate type, use the so called T layout where the sources of two cells on adjacent rows are mirrored along the center of a common source diffusion line and the sources of the all the memory transistors of the array are connected to a common terminal. During reading of the selected cell, the non selected memory transistors belonging to the selected bitline and which have been programmed to a conductive state (they conduct current even if abs(Vgs)<0) cannot be changed to a nonconductive during the read mode unless the voltage of the non selected wordlines can be set to be below V
ss
(for NMOS cells) or above V
cc
(for PMOS cells). Generation of these voltages complicates the design of the memories. As a result an uncontrolled amount of current (hereinafter called leakage current) flows through the selected bitline and the common source, making the correct reading of the state of the selected memory transistor very difficult.
This problem has been lessened by insuring that the memory transistor is never erased (for a NMOS cell) or programmed (for a PMOS cell) to a normally on state when the gate-source voltage is zero, or by adding the select gate to the memory transistor (split gate cell). A normally on MOS device is often called a depletion device.
An array configuration has been presented in U.S. Pat. No. 5,949,718 in which the common source of two adjacent rows is connected to two additional transistors whose gates are the wordlines of the rows and which are connected to a common potential (ground for the array described). Even without a split gate memory cell, the leakage current problem is reduced, but not completely eliminated. The reason is that when reading one cell, the source of the mirrored cell is also grounded. If this cell has been programmed to be normally on, it contributes current during reading and this make more difficult for the sensing circuitry to decide if the selected cell is on or off. The leakage problem is reduced as compared to the case of conventional arrays, which use a common source for the entire array, since the leakage is limited to one cell only. The solution of the problem is not to erase the memory cell into a normally on state, although in this case more off current can be tolerated.
Another problem with a conventional array using a stacked gate cell and a common source is referred to as a “drain turn-on” problem. As an example, in an array utilizing a NMOS memory cell, applying 6 V on the drain (the bitline) and 9 V on the wordline does the programming of the selected cell.
The wordline of the non-selected rows is kept at V
ss
, but the drains of all the cells connected to the selected bitline are biased at 6 V. The capacitive coupling between the drain and the wordline will bring the potential of the floating gate to value comprised between 0 and 6 V. The actual value depends on the geometry of the cell and can be easily such that the non-selected cells are turned on. In this case each non-selected cell on the selected bitline is going to draw current and the total amount of current required for programming is increased.
BRIEF DESCRIPTION OF THE INVENTION
According to one aspect of the present invention, a nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline.
According to other aspects of the invention, an array of split-gate nonvolatile memory cells is provided. The array is arranged as a plurality of rows and columns of split-gate memory cell transistors. The sources of the split-gate memory cell transistors in each pair of adjacent rows of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline.


REFERENCES:
patent: 4451748 (1984-05-01), Amrany
patent: 5949718 (1999-09-01), Randolph et al.
patent: 6243298 (2001-06-01), Lee et al.
patent: 6272046 (2001-08-01), Shimada
patent: 6288938 (2001-09-01), Park et al.
patent: 6310800 (2001-10-01), Takahashi
IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays,IEEE Standard 1005-1998,The Institute of Electrical and Electronics Engineers, Inc, Approved Jun. 25, 1998.

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