Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-05-21
2003-07-22
Ton, Dang (Department: 2666)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S229000
Reexamination Certificate
active
06597693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to networks and more particularly, to a system and method of controlling network traffic data in a switched network operating according to Ethernet (IEEE 802.3) protocol.
2. Background Art
Switched local area networks use a network switch for supplying data frames between network stations or other network nodes, where each network node is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) enabling network interfaces within each network node and the network switch to access the media. A network switch stores and forwards data frames received from transmitter nodes to destination nodes based on header information and the data in the received frames, including source and destination addresses. An external memory, such as an SSRAM, is used by the network switch to temporarily store the data frames as they are passed through the switch.
In particular, a multi-port network switch typically stores and fetches data frames stored in its external memory via read and write buses within the switch connected to each port through a port interface, an external bus, and an external bus interface connecting the read and write busses to the external bus. The multi-port switch may be used to interconnect network segments having different network data rates (i.e., wire rates), hence, individual ports within a multi-port network switch may need to accommodate a wide range of differing data transfer rates (e.g., 10 Mbps, 100 Mbps or 1 GBps). Hence, a port interface and associated port interface logic is needed to efficiently transfer data packets between the individual ports and the external memory without causing blocking (i.e., delay in transferring a data packet received at a switch port). The port interface must be capable of transferring data at rates corresponding to the particular data transfer rate of the port.
Hence, to achieve non-blocking conditions in all ports, each port interface architecture and logic corresponding to a particular port data transfer rate is optimized to efficiently accommodate the particular port data transfer rate. Consequently, the need for different port interface architectures and interface logic dependent upon the port data transfer rate correspondingly increases the cost and overall complexity of a network switch having ports of differing data transfer rates.
SUMMARY OF THE INVENTION
Hence, there is a need for a multi-port network switch having a common port interface architecture independent of the port data transfer rate to minimize the cost and complexity associated with each individual network switch, while maintaining non-blocking characteristics. In addition, there is a need for a common logic scheme for each port interface, also independent of the port data rate, to further minimize the cost and overall complexity of each network switch.
These and other needs are met by the present invention which provides a common architecture for all of the ports within a network switch that is scalable over a wide range of data rates. This scalability is accomplished through a common logic scheme that is independent of the port data rate by utilizing a “handshaking” protocol to control the data path without reference to the data rate.
According to one aspect of the invention, a network switch arrangement includes an external memory for temporarily storing data packets to be forwarded by the network switch and an associated external memory controller within the switch. Also within the switch, the network switch ports each have a predetermined transmission rate for receiving data packets from and transmitting data packets to external network nodes. A data packet transmission controller is associated with each network switch port for controlling the transmission of data packets between the external memory and the network switch ports. A state machine within the data packet transmission controller receives predetermined information from the external memory controller concerning data packets being either transmitted or received by the network switch port. Based on the predetermined information, the state machine issues a command signal to a scalable data path logic within the data packet transmission controller for controlling transmission of the data packets. The scalable data path logic is also configured to be scaled to the rate of transmission of data packets between the network switch port and the external memory based on the predetermined data rate of the network switch port.
The scalable data path logic affords the present invention scalability of the data path over a wide range of data rates may be achieved while maintaining a single, common logic architecture.
According to another aspect of the invention, a method of controlling a transmitting and receiving data path within a network switch port includes writing data received at the port to an external memory or reading data to be transmitted by the port from the external memory via the transmitting and receiving data path at a certain defined data rate. Additionally, a control signal is generated to control the transmitting and receiving data path based upon predetermined information concerning a particular data packet. Finally, the data rate of the transmitting and receiving data path is scaled to the certain defined data rate based upon the control signal.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5448558 (1995-09-01), Gildea et al.
patent: 5515376 (1996-05-01), Murthy et al.
patent: 5909564 (1999-06-01), Alexander et al.
patent: 6052751 (2000-04-01), Runaldue et al.
patent: 6233244 (2001-05-01), Runaldue et al.
Advanced Micro Devices , Inc.
Ton Dang
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