Common pass gate layout of a D flip flop

Details Common pass gate layout of a D flip flop Common pass gate layout of a D flip flop

2006-05-10

2008-12-16

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S204000, C257S206000, C257S369000, C257SE27107, C257SE27108

Reexamination Certificate

active

07465970

ABSTRACT:
A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

REFERENCES:
patent: 5079614 (1992-01-01), Khatakhotan
patent: 6838713 (2005-01-01), Gheewala et al.
patent: 2001/0052623 (2001-12-01), Kameyama et al.
patent: 2002/0074570 (2002-06-01), Possley
patent: 2006/0097294 (2006-05-01), Yamashita et al.

Affiliated with

Also associated with

Rating

Common pass gate layout of a D flip flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Common pass gate layout of a D flip flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Common pass gate layout of a D flip flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4023857