Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-04-13
2002-10-15
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C361S728000, C361S729000
Reexamination Certificate
active
06466472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a common module for DDR SDRAM and SDRAM. In particular, the invention achieves the object of a DDR SDRAM and SDRAM common layout without the need for an extra IC or increasing the cost.
2. Related Art
As the CPU (Central Processing Unit) is driven to high frequencies, the increases in the bus bandwidth and memory speed also become a key factor of the system efficiency. An analysis of the Rambus structure and the SDRAM-II, or DDR SDRAM (Double Data Rate Synchronous DRAM), indicates that both of them have the advantage of increasing data transmission rates.
On the other hand, since the DDR SDRAM structure is compatible with the current SDRAM structure, unlike Rambus which requires to redefine the socket standard, the application of the former is thus much easier than the later.
SDRAM (Synchronous DRAM) is a new model of the DRAM and has a much faster clock rate then conventional memory. Since it can be synchronous with the CPU bus and can simultaneously open two memory pages, the operation speed can reach 133 MHz.
The current Intel Pentium CPU series uses the 100 MHz and 133 MHz CPU buses, therefore the SDRAM can still support the system. However, future personal computers may use over 200 MHz buses, then the SDRAM will not be able to support the standard. Therefore, developing higher speed memory such as DDR SDRAM is more and more urgent.
Since the DDR SDRAM is able to support data transmissions according to the clock rates on both ends, the data transmission quantity of the memory chip is thus doubled. So it is also called the SDRAM II.
The state-of-art method for simultaneously supporting the DDR SDRAM and the SDRAM is to use a quick switch IC to control and switch the terminators to achieve the object of a DDR SDRAM and SDRAM common layout.
SUMMARY OF THE INVENTION
An object of the invention is to provide a common module for DDR SDRAM and SDRAM that achieves the goal of a DDR SDRAM and SDRAM common layout without the need of an extra quick switch IC.
After testing the disclosed common module, the terminators on a motherboard can be set to be between 220 &OHgr; and 1250&OHgr;. A preferred value is 330&OHgr;. Within the preferred range, both the DDR SDRAM and the SDRAM can function normally and the work current falls within the range allowed by the SDRAM controller.
REFERENCES:
patent: 6215686 (2001-04-01), Deneroff et al.
patent: 6347367 (2002-02-01), Dell et al.
patent: 6362996 (2002-03-01), Chang
patent: 6381164 (2002-04-01), Fan et al.
Birch & Stewart Kolasch & Birch, LLP
Giga-Byte Technology Co. Ltd.
Lebentritt Michael S.
Nguyen Van Thu
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