Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-10-08
2002-04-09
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06369729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of converter circuits and, more particularly, to high order modulator circuits.
2. Background of the Related Art
The use of analog-to-digital converters (A/D converters or ADCs) to convert analog signals into digital signals is well known in the art. State-of-the-art practice is to fabricate an ADC on a single integrated circuit chip. Generally, an ADC samples an analog signal at a sampling rate which is twice the highest frequency component being sampled. This is known as the Nyquist rate. The sampled signal is processed and converted into a digital format for output from the converter.
A particular type of ADC employs an oversampling technique in which the analog input signal is sampled at a much higher rate than the Nyquist rate. The higher sampling rate improves the performance of the ADC for signal conversion and processing. One commonly used oversampling type of ADC uses a delta-sigma (&Dgr;&Sgr;) modulator for oversampling the analog input. The oversampled output of the &Dgr;&Sgr; modulator is coupled to a decimator, which employs a low-pass filtering technique to extract the lower frequency components to generate a converted digital output signal at the Nyquist rate. The &Dgr;&Sgr; modulators generally employ multiple integrator stages for providing the signal conversion.
It is appreciated that a typical high order modulator for a mixed-signal circuit utilizes a large number of digital switches. For example, when switched capacitor sampling circuits are utilized to sample the input signal, four switches are typically used with the sampling capacitor for each stage of the modulator. In a fifth-order &Dgr;&Sgr; modulator, there are five integrator stages present, each with a switched capacitor input sampling circuit. When differential integrator stages are used, at least eight switches are typically required for the sampling operation of each integrator stage.
In order to reduce power consumption in a chip, devices are designed to operate at lower supply voltages. Low power devices are desirable for applications where power drain is a concern. A lap-top (or notebook) computer, which uses a battery power source, is an example. However, the switches may not turn on at these lower voltages, if the gate voltage is not appreciably different from the source/drain voltage. To alleviate this turn-on problem, prior art modulators use a voltage booster (such as a voltage doubler) to drive the gates of the switches to ensure that the switches turn on. However, boosting the voltage for switch activation increases the power consumption in the device, as well as increasing the area on the device to accommodate the boosting circuitry.
The present invention implements a technique which allows certain stages of the modulator to operate at lower voltages in order to reduce power consumption in a mixed-signal modulator.
SUMMARY OF THE INVENTION
A modulator comprised of a plurality of differential stages for converting an input signal is described. A range of the input to the modulator is such that the first stage requires a common mode voltage that requires a boosted supply voltage to clock the input transistor switches. The outputs of the downstream integrators are typically smaller so as to enable a common mode that is closer to either the supply voltage or its return. Accordingly, a non-boosted voltage can be utilized for the gate drive of the downstream integrator stages, which results in lower power consumption and less chip area for the voltage boost circuitry of the modulator, thus making the modulator implementation more power/area efficient at lower supply voltages.
REFERENCES:
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patent: 5654711 (1997-08-01), Fujimori
patent: 5818374 (1998-10-01), Tan
patent: 5886586 (1999-03-01), Lai et al.
Lansirinne M., et al.; “A 2.5V 50 MHz Delta-Sigma-Modulator for Digital Cellular Telephones”; Midwest Symposium on Circuits and Systems, U.S., New York, NY; IEEE, Aug. 3, 1997, pp. 1165-1168.
Rhode Jason
Srinivasan Vishnu S.
Blakely & Sokoloff, Taylor & Zafman
Cirrus Logic Inc.
Jean-Pierre Peguy
Lauture Joseph
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