Common-mode output sensing circuit

Details Common-mode output sensing circuit Common-mode output sensing circuit

1996-12-02

1999-04-13

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

327337, 341162, H03M 144

Patent

active

058942840

ABSTRACT:
A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).

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A. Karanicolas et al., IEEE Journal of Solid-State Circuits, "A High-Frequency Fully Differential BiCMOS Operational Amplifier", vol. 26, No. 3, Mar. 1991, pp. 203-208.

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