Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-08-30
2004-08-03
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S148000
Reexamination Certificate
active
06771102
ABSTRACT:
BACKGROUND
1. Technical Field
An embodiment of the present invention generally relates to a charge pump. More particularly, an embodiment of the present invention relates to a charge pump having a common mode feedback.
2. Discussion of the Related Art
Electronic circuits that provide clock signals are used in a wide range of data systems, such as computer systems and digital data communication systems. Such systems generally operate at relatively high frequencies at which data bandwidth is at a premium. A phase-locked loop (“PLL”) may be used, for example, as part of a clock recovery unit, to derive a clock signal from incoming data signals. For instance, a PLL may be used to synchronize, or de-skew, an internal control clock with respect to an external system clock.
A PLL may include a phase/frequency detector (“PFD”), a charge pump, a low-pass filter, and a voltage-controlled oscillator (“VCO”). The PFD compares two input signals, a reference signal from the external system clock and a feedback signal. The PFD generates phase error signals (“UP” and “DOWN”) that are a measure of the phase difference between the reference signal and the feedback signal. The charge pump generates control signals, based on the phase error signals from the PFD. The low-pass filter filters the control signals, which are then fed into the control input of the VCO. The VCO generates a periodic signal at a frequency which is controlled by the filtered phase error signal.
The high frequency at which data is communicated in data systems, and the need for higher reliability for the transmission of such data places significant requirements and low margins of error on PLLs. One source of errors in PLLs is the charge pump circuitry. For example, charge pumps are often comprised of CMOS transistor elements. The CMOS transistor elements often exhibit slight variations in performance due to mechanical manufacturing discrepancies. Such discrepancies may result in undesirable variations in the phase error signals. Additionally, variations in the power supply used to power or bias the transistor elements also may result in undesirable variations, or jitter, in the charge pump signal.
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patent: 6509801 (2003-01-01), Lao et al.
Woogeun Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” IEEE 1999, pp II-545 through II-548.
Savoj, et al., “A 10-Gb/s Linear Half-Rate CMOS CDR Circuit,” High-Speed CMOS Circuits for Optical Receivers, 2001, pp 86-89 and 106-109.
Behzad Razavi, “Operational Amplifiers,” Design of Analog CMOS Integrated Circuits, 2001, pp. 296-309.
Behzad Razavi, “Phase-Locked Loops,” RF Microelectronics, 1998, pp. 261-264.
Abidin Cindra W
Asmanis Georglos S
Intel Corporation
Nguyen Linh M.
Pillsbury & Winthrop LLP
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