Common mode bias voltage generator

Details Common mode bias voltage generator Common mode bias voltage generator

2000-04-26

2001-10-09

Nguyen, Matthew (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C327S530000

Reexamination Certificate

active

06300752

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to signal processing devices in telecommunication systems, and more particularly to a common mode bias voltage generator apparatus and method used in signal processing devices.
2. Description of Related Art
In many signal processing devices, such as a switched capacitor circuit, it is often necessary to generate bias voltages proportional to a supply voltage VCC or VDD. For example, to maximize a dynamic range of a differential amplifier, it may be desirable to generate a VCC/2 (or VDD/2) bias voltage to use as a common mode output reference.
Common mode bias voltages can be generated with many circuits. One circuit to generate a common mode bias voltage is a capacitively bypassed resistor divider. However, a simple resistor divider may not provide the best trade off of power dissipation and circuit area to meet the output impedance, settling time, and/or noise performance required for an intended or required use of a common mode bias voltage generator.
A simple resistor divider generally includes a couple of resistors serially connected to each other. To provide required power output, the output impedance of a resistor divider is often much higher, thereby significantly affects the settling time and noise performance of the entire system. To reduce the output impedance, a simple resistor divider is often buffered with a full-blown power amplifier to obtain required output power. This type of bias voltage generator may require an additional off-chip power amplifier. If a power amplifier is built on-chip, it would increase the size of the chip design and may be difficult to design in high speed applications. Further, this type of bias voltage generator is not the best trade, off of power dissipation and circuit area to meet the output impedance, settling time, and/or noise performance, etc.
In a switched capacitor circuit, a transient switch is often modeled as a resistor with a particular value. To obtain a better settling time and/or noise performance, it is generally desired to have a common mode bias voltage proportional to a supply voltage with a lower output impedance while using relatively little power and circuit area.
It is with respect to these and other considerations that the present invention has been made.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a common mode bias voltage generator apparatus and method.
The present invention solves the above-described problems by providing a common mode bias voltage generator apparatus and method which allow to generate bias voltages proportional to a supply voltage with a low output impedance while using relatively little power and circuit area.
One embodiment of the common mode bias voltage generator apparatus, in accordance with the principles of the present invention, includes a plurality of transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a low output impedance and a predetermined power requirement.
Still in one embodiment, the apparatus includes first, second, third, fourth, fifth, sixth transistors, first, second, and third resistors, wherein the first resistor and the first transistor are serially connected between a supply voltage and ground, the first resistor is coupled between the supply voltage and a drain of the first transistor, the drain and a gate of the first transistor are coupled to each other, a source of the first transistor is coupled to the ground, and the second resistor is coupled in parallel to the first transistor.
Further in one embodiment, the second and third transistors are serially connected between the supply voltage and the ground. A drain of the third transistor is coupled to a drain of the second transistor and to a gate of the third transistor. A source of the third transistor is coupled to the supply voltage. A source of the second transistor is coupled to the ground, and a gate of the second transistor is coupled to the gate of the first transistor.
Additional in one embodiment, the fourth transistor and the sixth transistor are serially coupled between the supply voltage and the ground. A source of the fourth transistor is coupled to the supply voltage, and a source of the sixth transistor is coupled to the ground. A drain of the fourth transistor and a drain of the sixth transistor are coupled to each other and are coupled to an output port of the apparatus. A gate of the fourth transistor is coupled to the gate of the third transistor. A gate of the sixth
Further in one embodiment, the third resistor and the fifth transistor are coupled between the output port and the ground. The third resistor is coupled between the output port and the drain of the fifth transistor. A gate of the fifth transistor is coupled to the gate of the second transistor. A source of the fifth transistor is coupled to the ground.
Still in one embodiment, a capacitor is coupled between the output port and the gate of the sixth transistor.
Yet in one embodiment, the first, second, fifth, and sixth transistors have the same gate-source voltage and the same drain current. The first and second resistors have the same resistance, and the third resistor has a half of the resistance of the first resistor. A drain current of the fourth transistor is twice of a drain current of the third transistor. An output voltage generated at the output port is a half of the supply voltage.
A method of generating a common mode bias voltage in accordance with the principles of the present invention includes providing a plurality of transistors, a plurality of resistors, and a supply voltage; and generating a half of the supply voltage with a predetermined output impedance and power requirement.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.


REFERENCES:
patent: 5218238 (1993-06-01), Nonaka et al.
patent: 5654663 (1997-08-01), McClure et al.
patent: 5808515 (1998-09-01), Tsuruoka et al.
patent: 5963057 (1999-10-01), Schmitt et al.
patent: 6008632 (1999-12-01), Sasaki

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