Common memory control system with two bus masters

Details Common memory control system with two bus masters Common memory control system with two bus masters

1983-05-03

1986-12-09

Shaw, Gareth D.

Boots, shoes, and leggings

365222, G06F 1316

Patent

active

046284826

ABSTRACT:
In accordance with the present invention, there is provided a data processing apparatus comprising an MPU which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means for latching said address signal, a memory which must be refreshed, and changeover means for connecting said memory to said MPU during a data signal period and connecting said memory to a refresh counter during remaining periods.

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Buettner, Crooks, Johnson, Saunders, "Transparent Refresh of Dynamic Memories", IBM Tech. Disc. Bulletin, vol. 23, No. 4, 9/80, pp. 1592-1602.

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