Common format for encoding both single and double precision floa

Details Common format for encoding both single and double precision floa Common format for encoding both single and double precision floa

1992-09-14

1993-12-07

Mai, Tan V.

Boots, shoes, and leggings

36471503, G06F 738

Patent

active

052688550

ABSTRACT:
A technique for encoding multiple floating point formats into a double precision floating point number by padding single word floating point numbers with zeros to form a 64-bit double word in a way that allows a single precision arithmetic logic unit to be built on top of a double precision arithmetic logic unit. The formatting circuitry of the invention requires only small differences in the hardware for single and double precision operations so as to simplify the arithmetic logic unit and the multiplier of the floating point processing units. The encoding technique of the invention includes right justifying the exponent and mantissa of the floating point number in a "common format" such that rounding of the mantissa need only occur in one place, thereby greatly simplifying the rounding procedure. The technique of the invention also removes multiplexers from critical speed paths in the floating point processing units when it is desired to accommodate multiple data formats.

REFERENCES:
patent: 3872442 (1975-03-01), Boles et al.
patent: 4831575 (1989-05-01), Kuroda
patent: 5038309 (1991-08-01), Priem et al.
patent: 5161117 (1992-11-01), Waggener, Jr.
DeLano et al., "A High Speed Superscalar PA-RISC Processor", Proceedings of the Compcon Spring 1992, Digest of Papers, San Francisco, CA. Feb. 24-28, 1992.

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