Common bus communication system in which the width of the addres

Details Common bus communication system in which the width of the addres Common bus communication system in which the width of the addres

1979-06-18

1981-08-25

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 704

Patent

active

042863210

ABSTRACT:
The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.

REFERENCES:
patent: 3972028 (1976-07-01), Weber et al.
patent: 4016545 (1977-04-01), Lipovski
patent: 4045782 (1977-08-01), Anderson et al.
patent: 4112490 (1978-09-01), Pohlman et al.
Brown et al., "Instructions for Byte Addressing Capability", IBM Tech. Dis. Bull., vol. 16, No. 3, Aug. 1973, pp. 812-815.

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